FinFET 2010s Adopt Multi Fin Transistor Design as New Sizing Paradigm

# FinFET (2010s): Step 9 — Adopt Multi-Fin Transistor Design as a New Sizing Paradigm

## 1. How Planar Designers Used to Size a Transistor

In every planar CMOS generation this project has covered, a circuit designer who needed more drive current simply drew a wider transistor: channel width W was a continuously adjustable layout parameter, and doubling W roughly doubled drive current for a fixed gate length and supply voltage.

## 2. Why That Lever No Longer Exists

FinFET's effective channel width per fin, established in Step 3 as roughly twice the fin height plus the fin width, is fixed by the process once fin height and width are set — no individual fin can be made wider or taller by a circuit designer's layout choice. Drive current can only be scaled in discrete steps, one additional whole fin at a time, because a transistor's effective width is now N_fin multiplied by that fixed per-fin value rather than a continuously drawn dimension.

## 3. Multi-Fin Transistors as the New Normal

A FinFET transistor is therefore specified by its fin count rather than by a drawn width: a 1-fin device, a 2-fin device, a 3-fin device, and so on, each delivering an integer multiple of the same base drive current. This is a genuinely new transistor-sizing paradigm for digital design — libraries characterize and offer transistors in discrete fin-count variants, and a designer who needs drive current between two fin counts must either accept the next one up or combine devices, rather than drawing an intermediate width.

## 4. What This Step Does and Does Not Cover

This step establishes fin-count quantization as the new sizing unit; it does not yet address how this quantization reshapes standard-cell library layout and SRAM bit-cell design specifically, which Steps 10 and 15 take up in turn.

Drive Current Becomes a Step Function of Fin Count, Not a Continuous Curve transistor drive current against sizing parameter, continuously drawn planar width versus quantized FinFET fin count planar MOSFET: drive current scales continuously and smoothly with drawn channel width W FinFET: drive current steps discretely, one fixed increment per added whole fin (1, 2, 3 fin...) a designer needing current between two fin counts must round up or combine devices process generation advances left to right across this chart no individual fin can be drawn wider or taller — N_fin is now the only sizing lever libraries characterize and offer transistors as discrete 1-fin, 2-fin, 3-fin variants
From Continuous Width to Discrete Fin Count the sizing paradigm shift this step introduces, carried forward into cell and SRAM design PLANAR: DRAWN WIDTH W is a continuous layout parameter — any drive current is reachable by drawing FINFET: FIXED PER-FIN WIDTH W_eff per fin is fixed by process geometry, not by a designer's layout choice SIZING BY FIN COUNT drive current scales only in discrete whole-fin steps — N_fin is the new lever standard-cell library and SRAM bit-cell redesign, forced by this quantization, follow in Steps 10 and 15

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