FinFET 2010s Scale Fin to Fin Pitch Across Successive Generations

# FinFET (2010s): Step 6 — Scale Fin-to-Fin Pitch Across Successive FinFET Generations

## 1. Pitch as a Separate Scaling Axis From Gate Length

Where planar scaling tracked a single dominant metric, gate length, FinFET scaling tracks fin pitch — the center-to-center spacing between adjacent fins — as a largely independent axis. Shrinking fin pitch packs more fins, and therefore more drive-current-per-area, into the same standard-cell footprint, even when gate length and fin height stay fixed.

## 2. The Generational Trend, From Introduction Through 10nm

Early tri-gate production at the 22nm logic node used fin pitches around 60 nanometers; successive 14nm and 10nm generations pushed fin pitch down into the high-20s and mid-20s of nanometers respectively, each reduction achieved mainly through the self-aligned patterning refinements Step 4 introduced rather than through gate-length scaling alone. Fin pitch, not gate length, became the metric foundries quoted most consistently when comparing FinFET node generations.

## 3. Why Pitch Scaling Has a Harder Floor Than Gate-Length Scaling Did

Each additional self-aligned patterning cycle used to shrink fin pitch further compounds overlay error and line-edge roughness, from Step 5's variability concern, more than the previous cycle did. Below roughly 24-25 nanometers of fin pitch, adjacent fins also begin to interact electrostatically and thermally in ways isolated fins did not, so pitch scaling runs into both a patterning-cost floor and a device-physics floor well before gate-length scaling alone would have stopped it.

## 4. What This Step Does and Does Not Cover

This step establishes fin pitch as a distinct, generation-over-generation scaling metric and names why it has diminishing headroom; it does not yet address the gate stack wrapped around these increasingly dense fins, which Step 7 takes up as the replacement-metal-gate requirement.

Fin Pitch Becomes the Generation-Over-Generation Scaling Metric minimum fin pitch at successive FinFET-era logic nodes, with each generation's reduction harder-won than the last fin pitch: roughly 60nm at 22nm-class introduction, falling through 14nm and 10nm generations patterning-cycle count and overlay budget required to reach each successive pitch below roughly 24-25nm fin pitch, patterning cost and fin-to-fin interaction both worsen process generation advances left to right across this chart fin pitch, not gate length alone, is the metric FinFET generations are most consistently compared by each additional self-aligned patterning cycle buys less pitch reduction than the one before it
Fin Pitch Across Three FinFET Generations the generational trend this step tracks, from tri-gate introduction through the 10nm node 22NM TRI-GATE introductory fin pitch near 60nm, the first production tri-gate generation 14NM fin pitch reduced into the high-20s of nanometers via refined SAQP patterning 10NM fin pitch reduced further into the mid-20s, approaching the patterning-cost floor fin pitch scaling has both a patterning-cost floor and a device-physics floor, discussed further in Steps 18-19

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