FinFET 2010s Confront Parasitic Capacitance from Raised Merged Source Drain

# FinFET (2010s): Step 12 — Confront Parasitic Capacitance Introduced by Raised, Merged Source/Drain

## 1. A Cost That Comes Bundled With Step 11's Fix

The raised, merged source/drain epitaxy Step 11 described solves a real series-resistance problem, but the larger epitaxial volume it creates sits closer to, and overlaps more of, the gate and contact structures around it than a minimal planar-style source/drain region would. That proximity is itself a new parasitic-capacitance source specific to this geometry.

## 2. Where the New Capacitance Comes From

Outer-fringe capacitance between the raised source/drain's larger volume and the gate electrode rises directly with how far the epitaxial growth extends toward the gate; and because adjacent fins' source/drain regions are now merged into a shared volume, capacitance between that shared region and the contacts, and between neighboring devices' now-closer source/drain volumes, both increase as well. None of these terms existed in the same form for a planar transistor's flatter, more separated source/drain geometry.

## 3. The Design Tradeoff This Reopens

Larger raised source/drain volumes reduce series resistance, from Step 11, but increase this parasitic capacitance; smaller, less-merged volumes do the reverse. Because switching delay depends on both resistance and capacitance together, process and design teams must jointly tune epitaxial growth volume and spacer thickness around the gate to land on a combined RC product that is actually faster than either extreme, not simply minimize one term in isolation.

## 4. What This Step Does and Does Not Cover

This step covers parasitic capacitance from the source/drain structure itself; a related but separate parasitic effect, fin-body depletion in the lightly doped channel, is covered next in Step 13 as a distinct consequence of FinFET's undoped-channel approach from Step 5.

Raised Source/Drain Trades Resistance for Fringe Capacitance parasitic series resistance and fringe/overlap capacitance plotted against raised source/drain epitaxial volume series resistance (falls as raised source/drain volume and contact area increase) fringe and merged-volume parasitic capacitance (rises as that same volume grows) the fastest combined RC product sits between the two extremes, not at either one process generation advances left to right across this chart merged fins' shared volume raises capacitance to contacts and to neighboring devices alike process and design teams must jointly tune epitaxial volume against spacer thickness
Where the New Capacitance Terms Come From three parasitic paths specific to raised, merged fin source/drain, absent from a flatter planar structure GATE FRINGE larger raised volume extends closer to the gate electrode than a minimal planar S/D would MERGED-VOLUME TO CONTACT a shared epitaxial volume spanning several fins couples more strongly to its contact NEIGHBOR-DEVICE COUPLING closer adjacent source/drain volumes couple capacitively to neighboring devices fin-body depletion, a separate parasitic effect from the undoped channel itself, follows in Step 13

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