FinFET vs GAAFET

FinFET vs GAAFET is the transistor architecture transition now underway across every leading-edge foundry: the gate stops wrapping three sides of a vertical silicon fin and starts surrounding the channel on all four sides as a stack of horizontal nanosheets. FinFETs carried the industry from 22 nm (Intel, 2011) down to 3 nm, but below that the ungated bottom of the fin leaks too much current to keep shrinking. Gate-all-around (GAA) nanosheet devices — Samsung calls them MBCFET, Intel calls them RibbonFET — restore full electrostatic control and are the device for 2 nm, Intel 18A, and everything beyond.

Electrostatic control is the whole story. A transistor is a switch: the gate must be able to shut the channel off completely. The more of the channel surface the gate touches, the better it wins that fight against the drain, which is simultaneously trying to pull the channel on. A planar MOSFET gates one side. A FinFET gates three — two sidewalls plus the top of the fin. A GAA nanosheet gates all four surfaces of every sheet in the stack. Each extra gated side buys back the control that short channel lengths take away.

Subthreshold swing — the figure of merit. Subthreshold swing (SS) is how many millivolts of gate voltage it takes to change the drain current by a factor of ten. Lower is better, because it means the device turns off harder at lower supply voltage:

At 300 K the $\frac{k_B T}{q}\ln(10)$ term equals 59.6 mV/dec — the Boltzmann limit no conventional MOSFET can beat. The parenthesized term is the penalty: $C_{dep}$ is the depletion capacitance the drain couples through, $C_{ox}$ is the gate oxide capacitance. Wrapping the gate around more of the channel drives $C_{dep}/C_{ox}$ toward zero. Production FinFETs land at 68–75 mV/dec; nanosheet GAA reaches 60–66 mV/dec, close enough to ideal that the same off-current is achievable at meaningfully lower $V_{DD}$.

DIBL — what leakage actually looks like. Drain-induced barrier lowering measures how much the drain voltage shifts the threshold voltage. High DIBL means the drain is reaching into the channel and turning the transistor on without the gate's permission. FinFETs at 3 nm run 45–60 mV/V; nanosheet GAA holds below 35 mV/V at the same gate length because there is no ungated path under the channel for the drain field to exploit. That margin is what lets the industry shorten the gate further instead of stalling.

Width quantization — the change designers feel. Effective channel width sets drive current, and the two architectures quantize it very differently:

A FinFET can only add drive current one whole fin at a time — a coarse, discrete step, since fin height and width are fixed by the process. A nanosheet's width is set by lithography, so a designer can dial $W_{sheet}$ continuously from roughly 8 nm to 50 nm. A narrow sheet gives a low-power, low-capacitance cell; a wide sheet gives a high-drive cell for timing-critical paths. Same mask layer, same process — the standard-cell library gets a tuning knob it never had with fins.

How a fab actually builds a nanosheet. The GAA flow reuses the FinFET toolset but adds four steps that have no FinFET equivalent, and all four are yield-critical:

1. Superlattice epitaxy. Grow alternating Si and SiGe layers — typically ~5 nm Si channels separated by ~8–10 nm Si₀.₇₀Ge₀.₃₀ sacrificial layers — with atomically abrupt interfaces. Thickness uniformity here becomes threshold-voltage uniformity later.
2. Fin patterning and dummy gate. The superlattice stack is etched into tall pillars using EUV lithography, then covered by a sacrificial poly-Si gate, exactly as in a FinFET replacement-gate flow.
3. Inner spacer formation. The SiGe is laterally recessed and the cavities refilled with a low-k dielectric such as SiBCN. Without this, the metal gate would sit directly against the source/drain epitaxy and the resulting gate-to-drain capacitance would erase the switching-speed gain. This step does not exist in FinFET.
4. Channel release and all-around gate. A highly selective vapor-phase etch strips every SiGe layer, leaving the Si sheets suspended on their source/drain anchors. Atomic layer deposition then fills each gap with HfO₂ and TiN/TiAl work-function metal — the moment the gate becomes gate-all-around.

The hard part is that released sheets are suspended nanoscale beams. They can sag or stick together, the selective etch must clear SiGe from gaps only a few nanometres tall without thinning the Si, and the ALD must fill those same gaps conformally. This is why GAA arrived a full node after it was theoretically ready.

Who ships what. The transition is staggered across the leading-edge foundries:

What comes after GAA. Nanosheets are not the end. The next structural move is CFET — complementary FET — which stacks the pMOS device directly on top of the nMOS device instead of placing them side by side, roughly halving standard-cell footprint again. CFET reuses the nanosheet channel and the channel-release step, which is one more reason the industry absorbed GAA's process complexity now rather than stretching FinFET further.

What it means for AI silicon. An AI accelerator is dominated by dense SRAM and enormous arrays of identical multiply-accumulate cells, and both are leakage-sensitive at scale: a die with hundreds of billions of transistors pays for every microamp of off-current a hundred billion times over. GAA's lower DIBL and steeper subthreshold swing let the same design run at lower $V_{DD}$, and dynamic power scales with $V_{DD}^2$. Continuous sheet-width tuning matters just as much — the wide sheets go into the timing-critical datapath while narrow sheets go into the surrounding logic, so the accelerator gets its clock speed without paying full leakage across the whole die. That combination, not raw density, is why 2 nm-class GAA is the substrate for the next generation of AI hardware.