nanosheet gate all around channel

**Nanosheet Gate-All-Around (GAA) Channel Formation** is **the advanced transistor fabrication process that creates vertically stacked horizontal silicon nanosheets fully surrounded by gate material, enabling superior electrostatic control and drive current density beyond the limits of FinFET architecture at sub-3 nm technology nodes**. **Superlattice Epitaxial Growth:** - **Si/SiGe Stack**: alternating layers of Si (channel) and SiGe (sacrificial) grown by reduced-pressure chemical vapor deposition (RPCVD) at 600-700°C - **Layer Count**: typically 3-4 nanosheet pairs for N3/N2 nodes; each Si channel 5-7 nm thick, SiGe sacrificial layers 8-12 nm thick - **Ge Concentration**: SiGe sacrificial layers contain 25-30% germanium to ensure high etch selectivity during channel release - **Thickness Uniformity**: within-wafer Si channel thickness variation must be <0.3 nm (3σ) to control threshold voltage—achieved through advanced temperature zoning in RPCVD chambers - **Defect Control**: total superlattice thickness of 80-120 nm must remain below critical thickness for strain relaxation to avoid misfit dislocations **Nanosheet Patterning and Fin Formation:** - **Fin Etch**: anisotropic reactive ion etching (RIE) patterns the Si/SiGe superlattice into fin structures with 25-30 nm pitch using EUV lithography - **Sidewall Profile**: fin sidewall angle must be 88-90° with surface roughness <0.3 nm RMS to ensure uniform channel width - **Aspect Ratio**: fin heights of 80-120 nm with widths of 15-25 nm yield aspect ratios of 4:1 to 8:1, requiring carefully tuned HBr/Cl₂/O₂ etch chemistry - **End Cap Control**: fin end profiles must be precisely shaped to minimize parasitic capacitance at nanosheet terminations **Sacrificial SiGe Removal (Channel Release):** - **Selective Etch Chemistry**: vapor-phase or wet HCl-based etching removes SiGe with >100:1 selectivity to Si channels—critical for preserving channel thickness and surface quality - **Etch Access**: etchant must penetrate through inner spacer openings (5-8 nm gaps) to reach buried SiGe layers uniformly - **Channel Bowing**: over-etching causes lateral thinning of Si channels; under-etching leaves SiGe residues that degrade gate oxide integrity - **Surface Passivation**: post-release hydrogen passivation at 400-500°C eliminates dangling bonds and surface traps on exposed Si channel surfaces **Gate Stack Wrapping:** - **Interfacial Oxide**: 0.3-0.5 nm chemical SiO₂ grown on all nanosheet surfaces via SC1 clean or ozone treatment - **High-k Dielectric**: 1.0-1.5 nm HfO₂ deposited by ALD with perfect conformality around released nanosheets—requires >150 ALD cycles with alternating TDMAH/H₂O pulses - **Work Function Metal**: TiN/TiAl/TiN stack for NMOS (4.1-4.3 eV) and TiN/TaN for PMOS (4.8-5.0 eV), each layer 1-3 nm thick - **Gate Fill**: tungsten or ruthenium fills remaining space between nanosheets (3-5 nm gaps), requiring nucleation-free bottom-up deposition **Nanosheet GAA channel formation represents the most significant transistor architecture transition since the introduction of FinFETs at the 22 nm node, delivering 15-25% performance improvement and 25-30% power reduction that are essential for continued semiconductor scaling below 3 nm.**