nanosheet channel formation
**Nanosheet Channel Formation** is the **multi-step epitaxy and selective-etch process that creates the horizontally-stacked, gate-all-around (GAA) silicon channels of nanosheet FETs — growing alternating layers of silicon and silicon-germanium, patterning them into fin-like stacks, and then selectively removing the SiGe sacrificial layers to release the silicon nanosheets for complete gate wrapping**.
**Why Nanosheets Replace FinFETs**
At the 3nm node and below, the fixed-height FinFET fin cannot provide enough drive current per unit footprint without either making fins taller (increasing aspect ratio beyond etch capability) or reducing fin pitch (below lithographic limits). Nanosheets solve this by stacking multiple horizontal channels vertically — effectively turning one tall fin into 3-4 individually-gated thin sheets, each fully surrounded by the gate.
**The Nanosheet Process Flow**
1. **Superlattice Epitaxy**: Alternating layers of Si (channel, ~5 nm thick) and SiGe (sacrificial, ~8-12 nm thick, Ge content ~25-30%) are epitaxially grown on the silicon substrate. Typically 3-4 Si/SiGe pairs are stacked.
2. **Fin-Like Patterning**: The superlattice stack is etched into narrow "fins" using the same SADP/SAQP or EUV techniques as FinFET fin patterning.
3. **Dummy Gate Formation**: A sacrificial polysilicon gate wraps around the stack, defining the channel length.
4. **Inner Spacer Formation**: After source/drain cavity etch, the exposed SiGe layers are laterally recessed (selective isotropic etch of SiGe vs. Si). The resulting cavities are filled with a dielectric (SiN or SiCO) to form inner spacers that electrically isolate the gate from the source/drain.
5. **SiGe Release (Channel Release)**: After dummy gate removal, the remaining SiGe sacrificial layers are selectively etched away using a highly selective vapor or wet etch (e.g., vapor-phase HCl or aqueous peracetic acid). The silicon nanosheets are now free-standing, suspended between the source and drain.
6. **Gate Stack Deposition**: High-k dielectric (HfO2, ~1.5 nm) and work-function metals (TiN/TaN/TiAl) are deposited conformally around all surfaces of each released nanosheet using ALD.
**Critical Challenges**
- **Etch Selectivity**: The release etch must remove SiGe with >100:1 selectivity over Si to avoid thinning the nanosheets. Even 0.5 nm of silicon loss shifts Vth and reduces drive current.
- **Sheet-to-Sheet Uniformity**: All 3-4 nanosheets must have identical thickness, width, and gate dielectric coverage. The bottom sheet sees different etch and deposition environments than the top sheet due to geometric shadowing.
Nanosheet Channel Formation is **the most complex front-end process sequence in semiconductor history** — turning a simple stack of alternating crystal layers into the suspended, gate-wrapped channels that carry every electron in the GAA transistor era.