gate all around nanosheet

**Gate-All-Around (GAA) Nanosheet Transistor Process** is the **next-generation transistor architecture succeeding FinFET at the 3 nm node and beyond — where the gate wraps completely around multiple stacked horizontal silicon nanosheets (channels), providing 4-sided electrostatic control that eliminates the fin width-dependent performance of FinFETs and enables variable-width channels through nanosheet width modulation, offering 15-25% performance improvement or 25-30% power reduction over FinFET at equivalent nodes**. **Nanosheet Process Flow** 1. **Superlattice Epitaxy**: Alternate layers of SiGe (sacrificial, ~5-8 nm) and Si (channel, ~5-7 nm) grown epitaxially on the substrate. 3-4 Si/SiGe pairs form the nanosheet stack (total stack height: 40-60 nm). 2. **Fin Patterning**: The superlattice stack is etched into fin-like structures using multi-patterning or EUV. Defines the nanosheet width (20-100+ nm), which directly controls drive current — unlike FinFETs where fin width is fixed. 3. **Dummy Gate Formation**: Polysilicon dummy gate deposited and patterned over the nanosheet stack, defining the gate length. 4. **Inner Spacer Formation**: After S/D recess etch, the exposed SiGe layers are selectively recessed laterally (isotropic etch selective to SiGe over Si). A dielectric (SiN or SiCO) fills the recessed cavities, forming inner spacers that isolate the gate from S/D regions and control parasitic capacitance. This is the most challenging new process step — uniform recess and fill across all nanosheet layers. 5. **S/D Epitaxy**: Epitaxial SiGe (PMOS) or Si:P (NMOS) grown from the exposed nanosheet edges. Must merge across all channel layers while maintaining crystal quality. 6. **Channel Release**: After ILD deposition and dummy gate removal, the SiGe sacrificial layers are selectively removed (HCl vapor or wet etch with high selectivity to Si). This "releases" the Si nanosheets, creating free-standing horizontal channels. 7. **Gate Stack Deposition**: High-k dielectric (HfO₂, ~1.5 nm) conformally deposited around all surfaces of the released nanosheets. Work function metals (TiN, TiAl, TiN stack) and gate fill metal (W or Al) deposited in the spaces between and around the nanosheets. **Critical Challenges** - **Channel Release Selectivity**: SiGe removal must be >1000:1 selective to Si to avoid thinning the channel nanosheets. Even 0.5 nm of Si loss shifts threshold voltage significantly. - **Gate Fill**: The spaces between nanosheets (~8-10 nm vertically) must be completely filled with work function metals without voids. Atomic Layer Deposition (ALD) is mandatory for conformal coverage in these extreme aspect ratios. - **Nanosheet Uniformity**: Thickness variation across the wafer and between sheets in the stack directly impacts threshold voltage and drive current matching. GAA Nanosheet Process is **the transistor architecture that extends Moore's Law beyond FinFET limits** — sacrificing process simplicity for superior electrostatic control and design flexibility, with Samsung (3 nm GAA, 2022) and TSMC/Intel (2 nm, 2025) leading volume production.