inner spacer gaa

**Inner Spacer Formation** is the **critical process module in Gate-All-Around (GAA) nanosheet transistors where the SiGe sacrificial layers are laterally recessed between the gate and source/drain regions, and the resulting cavities are filled with a low-k dielectric — creating the insulating barriers that prevent capacitive coupling between the gate metal and the heavily-doped source/drain, which would otherwise devastate switching speed and dynamic power**. **Why Inner Spacers Are Necessary** In a FinFET, the gate sidewall spacer is a simple vertical film on each side of the gate. In a nanosheet device, the gate wraps between the stacked channels — it extends laterally toward the source/drain in the space previously occupied by the SiGe sacrificial layers. Without an inner spacer filling that cavity, the gate metal would be separated from the source/drain by only the thin high-k dielectric, creating parasitic gate-to-S/D capacitance (Cgd) large enough to halve the transistor's effective switching speed. **Process Sequence** 1. **Source/Drain Cavity Etch**: After dummy gate formation and outer spacer deposition, an anisotropic etch removes the superlattice stack in the source/drain regions, exposing the cross-section of the alternating Si/SiGe layers. 2. **Lateral SiGe Recess**: An isotropic selective etch (vapor-phase HCl, or a controlled wet etch) removes the SiGe layers laterally, tunneling inward under the gate spacer by a controlled 5-8 nm from each side. This creates cavities between the silicon nanosheets. 3. **Dielectric Backfill**: A conformal low-k dielectric (SiN, SiCN, or SiOCN) is deposited by ALD to fill the cavities. The fill must be perfectly conformal to reach the innermost cavities between tightly-spaced nanosheets. 4. **Etch-Back**: An isotropic etch removes excess dielectric from all surfaces except the lateral cavities, leaving the inner spacer plugs in place. **Engineering Challenges** - **Recess Depth Control**: The lateral SiGe recess depth must be uniform (±0.5 nm) across all nanosheet layers and across the wafer. Under-recessing leaves residual SiGe that creates gate-S/D leakage; over-recessing enlarges the gate length beyond design intent. - **Cavity Fill in Tight Spaces**: The cavity is only 8-12 nm tall (the SiGe layer thickness) and 5-8 nm deep. ALD must deposit a pinch-off-free fill in this extreme aspect ratio. Voids in the inner spacer create parasitic capacitance pockets. - **Dielectric Choice**: Lower-k dielectrics reduce Cgd but have weaker mechanical properties and may not withstand subsequent high-temperature processing (S/D epitaxy at 600-700°C). SiCN (k ~4.5-5.0) balances electrical and thermal requirements. Inner Spacer Formation is **the process step that makes GAA transistors electrically viable** — without it, the capacitive penalty of wrapping the gate between stacked channels would erase the drive current benefit that motivated the nanosheet architecture.