inner spacer

**Inner Spacer Formation for Gate-All-Around Nanosheets** is the **process of creating thin insulating spacers between the Si/SiGe channel and metal gate — typically via selective etch of a Si/SiGe superlattice and ALD dielectric deposition — reducing fringing capacitance and enabling superior gate control in nanowire/nanosheet architectures**. This technique is essential for sub-3 nm logic and analog circuits. **Si/SiGe Superlattice Etch Strategy** In GAA nanosheet transistors, the channel consists of stacked Si and SiGe layers (alternating ~5-10 nm thickness). Selective etching removes SiGe layers preferentially (using HCl vapor or Cl₂ plasma) to create recesses around the Si channel. The etch selectivity (SiGe:Si ratio >50:1) is achieved by exploiting the lower thermal decomposition temperature of SiGe vs Si. Etch depth is carefully controlled to define the final nanosheet thickness and width. **ALD Dielectric Fill** After recessing, atomic layer deposition (ALD) fills the voids with high-k dielectric (SiO₂, SiN, or SiBCN) and serves as the inner spacer. ALD conformality ensures uniform thickness (1-3 nm typical) on high-aspect-ratio features. SiO₂ offers superior interface quality (low Dit) but lower k value; SiBCN provides intermediate properties. Multiple ALD cycles enable precise thickness control in sub-nm increments. **Etch Back for Inner Spacer Definition** Following dielectric fill, a controlled etch back (RIE using CF₄/H₂ or similar chemistry) removes the dielectric from the bottom of recesses and recess sidewalls, leaving a thin spacer on the Si nanosheet perimeter. This etch is stopped precisely to achieve target spacer thickness (~1-2 nm). Overetch removes too much spacer (increasing capacitance); underetch leaves excess dielectric (increasing parasitic capacitance between gate and channel). **Capacitance Reduction and Gate Control** Inner spacers physically separate the metal gate from the Si channel, reducing the electric field crowding near the channel edge. This reduces parasitic fringing capacitance (gate-to-Si/SiGe capacitance), directly decreasing the effective oxide thickness (EOT) and improving subthreshold swing (SS). The spacer also provides electrostatic decoupling, enabling independent biasing of adjacent nanosheets in vertically stacked devices. **Uniformity and Process Control** Spacer thickness uniformity across the nanosheet perimeter is critical — variations cause threshold voltage (Vt) mismatch between corners and center. Plasma etch uniformity, ALD precursor diffusion uniformity, and selective etch endpoint control are key variables. Spacer thickness variation target is <0.2 nm 3-sigma. Non-uniformity degrades device matching and increases leakage variability. **Comparison with FinFET External Spacers** FinFET external spacers are used to separate the gate from S/D regions (not the channel), typically 10-20 nm SiN via plasma deposition and etch. Inner spacers in GAA nanosheets are fundamentally different — they define the channel-to-gate distance itself, making them 5-10x thinner. This enables lower EOT and better subthreshold swing in nanosheets vs FinFETs. **Impact on Short-Channel Effects** The inner spacer thickness directly affects susceptibility to short-channel effects (SCE): DIBL, subthreshold swing, and leakage. Thinner spacers allow the metal gate to better couple to and control the channel, improving SS (target <60 mV/dec at 1 nm EOT). However, very thin spacers (<1 nm) risk tunnel leakage through the dielectric. **Summary** Inner spacer formation is a transformative process in GAA transistor technology, enabling precise control of the channel-to-gate distance and unlocking superior electrostatic properties. The combination of selective SiGe etching, conformal ALD deposition, and controlled etch back creates the foundation for 2 nm and beyond technology nodes.