gaa inner spacer
**GAA Inner Spacer Formation** is the **critical process step in gate-all-around (GAA) nanosheet transistor fabrication that creates dielectric spacers between the gate metal and the source/drain regions inside the nanosheet stack** — formed by selectively recessing the SiGe sacrificial layers from the channel edge, then depositing and etching back a low-k dielectric to fill the recess, providing electrical isolation that controls gate-to-source/drain capacitance and prevents gate metal from shorting to the S/D epitaxy.
**Why Inner Spacers Are Needed**
- GAA/nanosheet: Multiple horizontal Si channels stacked vertically, surrounded by gate metal.
- Without inner spacer: Gate metal directly touches S/D epitaxy → short circuit → device fails.
- With inner spacer: Dielectric barrier between gate and S/D → electrical isolation.
- Capacitance: Inner spacer material and thickness directly control Cgd (gate-drain capacitance) → affects speed.
- Low-k spacer: SiOCN or SiN → lower Cgd → faster switching.
**Inner Spacer Formation Process**
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**Critical Process Steps**
| Step | Challenge | Requirement |
|------|-----------|-------------|
| SiGe recess | Selectivity to Si (>30:1) | Uniform lateral etch depth |
| Recess depth control | Over-recess → thin spacer; under-recess → thick spacer | ±1nm precision |
| Dielectric deposition | Must fill narrow recess conformally | ALD preferred (< 1nm conformality) |
| Etch-back | Remove from Si surfaces, keep in recess | Isotropic, selective to Si |
**SiGe Selective Recess**
- Chemistry: Vapor-phase HCl at 500-600°C or wet etch (peracetic acid/H₂O₂).
- Selectivity: SiGe etches >30× faster than Si (Ge promotes etch rate).
- Recess depth: Typically 5-10nm → determines inner spacer thickness.
- Uniformity: Must be identical for all SiGe layers in stack → same recess depth top to bottom.
- Higher Ge content: Easier selectivity but different lattice → affects channel stress.
**Inner Spacer Material Options**
| Material | k value | Pros | Cons |
|----------|---------|------|------|
| SiN | 7.0 | Robust, well-characterized | High k → higher Cgd |
| SiOCN | 4.5-5.5 | Low k → better speed | Less etch resistance |
| SiOC | 4.0-5.0 | Lowest k | Poor mechanical stability |
| SiBCN | 5.0-6.0 | Good etch selectivity | Complex deposition |
**Impact on Device Performance**
- Thicker inner spacer: Lower Cgd → faster AC performance, but higher series resistance.
- Thinner inner spacer: Lower resistance, but higher Cgd → slower.
- Optimal: 5-7nm spacer thickness balances speed and resistance.
- k value: Moving from SiN (k=7) to SiOCN (k=5) improves ring oscillator speed by 5-8%.
GAA inner spacer formation is **the most challenging new process module introduced with nanosheet transistors** — requiring selective lateral etching, conformal dielectric fill, and precise etch-back all within a 5-10nm cavity buried inside a multi-layer stack, where the spacer thickness and material directly determine the transistor's speed-power trade-off, making inner spacer engineering the critical differentiator between competitive and non-competitive GAA process technologies.