flip chip bump

**Flip Chip Bumping** is the **process of forming solder or copper pillars on chip I/O pads that enable direct electrical and mechanical connection to a substrate without wire bonding** — the standard interconnect method for high-performance ICs requiring high I/O count and short interconnect length. **How Flip Chip Works** 1. **Bump Formation**: Deposit solder or Cu pillars on chip bond pads (UBM first). 2. **Flip**: Invert chip so bumps face down toward substrate. 3. **Align**: Optical/IR alignment of bumps to substrate pads. 4. **Reflow**: Heat to melt solder → bonds form between chip bumps and substrate. 5. **Underfill**: Dispense and cure epoxy between chip and substrate for mechanical strength. **C4 Bump (Controlled Collapse Chip Connection)** - IBM's original flip chip technology (1960s, still widely used). - Eutectic SnPb or lead-free SnAgCu solder balls, 100–250 μm pitch. - Self-centering: Liquid solder surface tension aligns chip during reflow. - Typical bump height: 80–120 μm. **Copper Pillar Bumps** - Electroplated Cu column + thin solder cap (SnAg or SnAgCu). - Fine pitch: 40–100 μm (vs. C4's 100–250 μm). - Lower solder volume → reduced bridging risk at fine pitch. - Better electromigration resistance than pure solder. - Standard for <28nm devices: Apple A-series, Qualcomm, AMD CPU/GPU. **Under Bump Metallization (UBM)** - Adhesion layer (Ti or TiW) + barrier layer (Ni) + wettable layer (Au or Cu). - Prevents Al pad corrosion, promotes solder adhesion, blocks Cu/Al interdiffusion. **Microbump (2.5D/3D IC)** - For die-to-die bonding: 10–40 μm pitch. - Used in HBM (High Bandwidth Memory), TSMC CoWoS packages. Flip chip bumping is **the enabling technology for high-density chip-to-package interconnects** — essential for every modern high-performance processor, GPU, and networking chip.