wafer bumping process c4

**Wafer Bumping and Flip-Chip** technologies are **solder/copper interconnection processes enabling face-down die bonding with fine-pitch capability (scaling from 200 µm C4 to <10 µm hybrid bonding)**. **C4 (Controlled Collapse Chip Connection):** - Solder bump: electroplated SnPb or SnAg on top of UBM (under-bump metallurgy) - Collapse mechanism: reflow melts solder, surface tension pulls die down - Pitch: traditional 200 µm, fine-pitch versions 150-100 µm - Process: pattern resist, evaporate/plate UBM (Au/Ni/Cu), plate solder, reflow - Advantages: mature, proven reliability, multiple suppliers **Copper Pillar Technology:** - Copper electroplating: plated Cu column (height 20-80 µm, diameter 20-50 µm) - Solder cap: thin SnAg solder on top of Cu pillar - Pitch advantage: sub-100 µm pitch enabling finer interconnect than C4 - EM reliability: Cu higher melting point vs solder-only bump - Cost: plating complexity vs C4 simplicity **Bump Electrolytic Plating Process:** - Seed layer: evaporated Ti/Cu provides initial conductivity - Resist patterning: photoresist defines bump locations (pitch-dependent) - Plating: Cu or Ni electrochemically deposited - Over-plating: metal grows column shape - Resist strip: photoresist removal, optional barrier removal (Ti/Cu etched) - Solder plate: SnAg electroplated on top (if needed) **Microbump for 3D/Advanced Packaging:** - Pitch scaling: <50 µm pitch possible (<10 µm hybrid bonding research) - Aspect ratio: height-to-width ratio critical (>1 preferred for coplanarity) - Coplanarity requirement: all bumps same height ±2 µm (affects yield) - Bumping tool precision: placement accuracy determines assembly yield **Underfill Process:** - Capillary underfill: low-viscosity capillary flow into bump gap (no vacuum needed) - Molded underfill: underfill overmold dies (more expensive, better reliability) - Purpose: mechanical reinforcement (thermal cycling stress), moisture barrier - Cure: UV initiation or thermal cure depending on resin chemistry **Flip-Chip Assembly Integration:** - Bump thermal compression bonding (TCB): heated tool applies force during reflow - Interconnect uniformity: ensures simultaneous bump contact - Rework challenge: unlike wire-bond, flip-chip difficult to repair (expensive) - Yield improvement: automated optical inspection (AOI) for bump placement QA **Reliability Testing (JEDEC):** - Thermal cycling: -40°C to +125°C cycles (1000+ cycles expected) - Drop test: mechanical shock 2 meters (consumer electronics standard) - HTOL (high-temperature operating life): functional test at 85°C/85% RH - FTAB (fluid thermal aging bucket): moisture absorption stress Wafer bumping technology directly enables chiplet integration and 3D stacking—progress in pitch scaling and reliability remains bottleneck for sub-100 µm pitch mainstream adoption.