floating point
**Floating point represents real-valued approximations with a sign, exponent, and significand so dynamic range and precision share a fixed bit budget.** Floating formats define numerical behavior, memory traffic, tensor-core throughput, convergence, reproducibility, and energy for scientific and AI workloads. IEEE 754 specifies major binary formats, rounding, signed zero, subnormal numbers, infinities, NaNs, and exception behavior, while accelerator formats add choices such as BF16, TF32, and FP8 E4M3 or E5M2. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. A format claim states storage and compute formats, accumulator width, rounding, denormal handling, saturation, NaN propagation, conversion points, scaling, and accepted error.
**Architecture, quantitative model, and operating behavior.** FP32 has one sign, eight exponent, and twenty-three explicit fraction bits; BF16 keeps FP32-like exponent range with seven fraction bits; FP16 uses five exponent and ten fraction bits; FP8 divides its tiny budget between E4M3 precision and E5M2 range. TF32 uses FP32 storage/range with reduced multiply precision on supported tensor operations. The exponent scales magnitude and the significand resolves nearby values. Spacing grows with magnitude, so addition can lose small terms and operations are generally non-associative. Round-to-nearest ties-to-even is common; fused multiply-add rounds once after multiplication and addition. FP64 supports demanding numerical science, FP32 general compute, BF16 training range, FP16 compact precision, FP8 high-throughput training/inference with scaling, and mixed precision stores, computes, and accumulates in different formats. Useful analysis separates arithmetic, memory hierarchy, interconnect, storage, control, and queuing. It counts operations and bytes at each boundary, identifies dependencies and reuse, estimates ideal ceilings, and then uses counters and traces to explain the gap between the model and measurement. Ratios without a clearly named numerator and denominator invite invalid comparisons. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints.
**Implementation, hardware mapping, and bottlenecks.** Use stable algorithms, loss or tensor scaling where appropriate, wider accumulation, guarded reductions, master weights when needed, and explicit conversions. Autocast policies require validation per operator rather than assuming every layer tolerates the same format. Halving bits reduces storage and bandwidth and allows more arithmetic lanes, but actual speedup depends on supported tensor-core modes, conversion, alignment, accumulation, and whether memory or compute is limiting. Overflow, underflow, cancellation, absorption, NaN propagation, flush-to-zero, non-associative parallel reductions, stochastic nondeterminism, and falsely treating BF16 as more precise than FP16 are common hazards. Begin with a correct reference and representative shapes. Profile end to end, classify the dominant resource, inspect kernel and system timelines, change one bottleneck at a time, and remeasure because optimization moves pressure elsewhere. Tiling, fusion, batching, vectorization, layout, precision, compression, overlap, prefetch, sharding, and algorithm choice are useful only when they reduce the limiting resource. The execution path spans registers, local SRAM and caches, HBM or GDDR, host DRAM, PCIe or coherent links, scale-up fabric, network, and storage. Compute units consume tensors only when compilers and kernels issue enough independent work and the hierarchy supplies operands. Package wiring, memory stacks, clocks, voltage, thermal headroom, and power delivery determine sustained limits. Frequent mistakes include quoting peak instead of achieved rates, omitting data conversion and transfer, measuring a cached toy input, timing asynchronous work without synchronization, mixing decimal and binary units, ignoring warmup or throttling, changing precision or quality, averaging away tails, and optimizing a component that is not on the critical path.
**Measurement, validation, and engineering controls.** Use high-precision references, unit-in-last-place and relative error, adversarial magnitudes, NaN/Inf/subnormal cases, reduction-order sweeps, convergence comparisons, and reproducibility tests across devices and compilers. Range, epsilon, significant digits, overflow and underflow rate, scaling margin, error norms, convergence, quality, throughput, bandwidth, memory, and energy matter. Instrument per-layer ranges and nonfinite values, bisect precision policies, preserve failing inputs, and compare intermediate tensors rather than only final loss. Verification combines analytical bounds, microbenchmarks, hardware counters, kernel timelines, end-to-end traces, scaling sweeps, sensitivity to batch and shape, cold and warm runs, long-duration thermal tests, correctness comparisons, fault and congestion tests, and independent reproduction. Roofline and queueing models guide diagnosis but must be calibrated against the deployed machine. Benchmark code, datasets, model and compiler artifacts, drivers, firmware, topology, clock and power settings, environment, commands, raw samples, counter traces, and analysis notebooks remain versioned. Continuous tests detect regressions in quality, latency, throughput, bandwidth, memory, power, and cost, with thresholds chosen from variance rather than a single run. Published comparisons disclose configuration, exclusions, tuning effort, measurement boundary, quality criteria, and uncertainty. Energy and carbon claims distinguish chip, IT, and facility boundaries and avoid extrapolating one benchmark to all workloads. Owners review regressions and retain evidence sufficient to reproduce decisions.
| Format | Bit layout | Range character | Precision character | Common AI role |
|---|---|---|---|---|
| FP64 | 1/11/52 | Very wide | About 16 decimal digits | Reference/scientific |
| FP32 | 1/8/23 | Wide | About 7 digits | Baseline/accumulation |
| BF16 | 1/8/7 | FP32-like range | Low precision | Training/activation |
| FP16 | 1/5/10 | Narrower | More fraction than BF16 | Training/inference |
| FP8 E4M3 | 1/4/3 | Moderate | More FP8 precision | Forward tensors |
| FP8 E5M2 | 1/5/2 | Wider | Lower precision | Gradients/dynamic values |
| TF32 | FP32 storage, reduced multiply | FP32-like | Tensor multiply compromise | Accelerated FP32 GEMM |
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**Selection and system-level application.** Use FP64 for sensitivity that needs it, FP32 as a reliable baseline, BF16 for robust training range, FP16 with scaling where supported, and FP8 only with calibrated scaling and wider accumulation. AI training and inference, simulation, graphics, signal processing, finance, control, and numerical libraries depend on floating-point choices. Format interacts with algorithms, initialization, loss, optimizer, reductions, compiler fusion, hardware modes, communication, checkpoint storage, and evaluation tolerance. Optimization is a system exercise across algorithms, precision, kernels, compiler, runtime, accelerator, memory, interconnect, scheduler, serving policy, cooling, and facility limits. Removing one ceiling often exposes another, so architecture decisions should optimize time and energy to a useful result rather than an isolated metric. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.