floorplan constraints

**Floorplan Constraints** are the **rules and guidelines that govern the placement of major functional blocks within the chip boundary** — determining macro placement, power domain boundaries, IO placement, and routing channel allocation before detailed cell placement begins. **Floorplan Elements** - **Die boundary**: Total chip dimensions determined by target area and package constraints. - **Core area**: Active logic area inside die — surrounded by IO ring. - **Power domains**: Separate voltage islands for power gating (MTCMOS blocks). - **Hard macros**: SRAMs, embedded memories, analog blocks — fixed size, must be placed first. - **Soft macros**: Hierarchical logic blocks — can be resized during implementation. - **IO pad placement**: Input/output pads arranged around core perimeter. **Hard Macro Placement Rules** - **Alignment**: Macros must align to site grid (typically 2x standard cell height). - **Abutment**: Memory banks often abutted for shared power rails. - **Orientation**: SRAMs have preferred orientation for bit-line timing. - **Channel width**: Minimum routing channel between macros — prevent congestion chokepoint. - Rule: ≥ 10μm channel for M1–M4; ≥ 20μm for full routing clearance. - **Halo (keepout)**: Buffer zone around macro where standard cells cannot be placed — prevents timing and DRC issues at macro boundary. **Floorplan Quality Metrics** - **Utilization**: Total standard cell area / core area. Target: 60–75%. - > 80%: Routing congestion risk. - < 50%: Wasted area, longer wires, higher power. - **Aspect ratio**: Width/height. Target: 0.8–1.3 (near square). Extreme AR → long power/clock distribution. - **Macro channel congestion**: Verify routing resource between macros before proceeding. **Power Domain Constraints** - Separate voltage rails for each power domain. - Level shifter and isolation cell placement at domain boundaries. - Power switches (MTCMOS) placed at power domain boundary rows. Floorplanning is **the most impactful decision in physical design** — a poor floorplan creates timing, congestion, and power problems that cannot be fixed downstream, while a well-planned floorplan makes every subsequent step smoother and faster to close.