floorplan
**A chip floorplan turns an abstract netlist into a physically credible arrangement of silicon.** It defines die and core dimensions, places large macros and I/O, reserves channels, establishes power delivery, and creates the geometric conditions under which placement, clocking, routing, timing closure, thermal control, and manufacturing can succeed. A weak floorplan pushes impossible congestion and long wires downstream; a strong one exposes tradeoffs early, when architecture can still change.
**Floorplanning is constraint reconciliation.** Memory wants adjacency to its consumers, high-speed interfaces want package-facing edges, analog blocks want quiet neighborhoods, power grids want regular coverage, and routing wants open channels. Those preferences cannot all win. The engineer searches for a topology whose worst risks have explicit margin, using early physical synthesis and analysis rather than arranging rectangles only for visual neatness.
| Floorplan decision | Primary benefit | Common failure if overused | Early evidence |
|---|---|---|---|
| Higher utilization | Smaller die area | Congestion and timing detours | Global-route overflow |
| Macro clustering | Short local buses | Pin-access hot spots | Fly-line and pin-density maps |
| Wider channels | Routability and power access | Added area and wire length | Trial-route congestion |
| Centralized shared block | Balanced logical access | Long global fanout | Estimated latency and buffering |
| More voltage islands | Energy optimization | Level-shifter and grid complexity | Power-state and crossing audit |
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**Die size begins with area but is rarely determined by area alone.** If (A_{cells}) is placed standard-cell area and (U) is target utilization, a first estimate is
$$A_{core} \ge \frac{A_{cells}}{U} + A_{macros} + A_{reserved}$$
Reserved area includes halos, channels, tap and endcap cells, decoupling, spare cells, power structures, and physical-only requirements. At high utilization, small inaccuracies become costly because whitespace is the resource used for buffering, timing repair, clock cells, and routing detours. A design may instead be pad-limited: the perimeter needed for I/O cells, bumps, seals, or package escape sets dimensions even when logic could fit in a smaller core.
Aspect ratio changes wire distributions and package fit. A long narrow core can shorten one dominant datapath while lengthening orthogonal routes. Rectangular dies may improve reticle or wafer utilization for a product family, but extreme shapes complicate power uniformity and clock latency. Die dimensions must also respect scribe lanes, seal rings, edge exclusions, reticle limits, and packaging tolerances.
**Macro placement is the defining act of most floorplans.** SRAMs, register files, analog blocks, PHYs, and hard IP cannot be spread like standard cells. Their size, orientation, pin sides, blockage layers, power connections, and timing relationships shape the remaining placement field. Connectivity fly-lines and weighted dataflow graphs help reveal natural neighborhoods. A macro should generally present its active pins toward connected logic and leave enough channel width for the estimated bus plus power and clock resources.
Halos keep standard cells and routes away from difficult macro edges. Routing blockages reserve layers where pins or internal shapes prevent safe passage. Notches and narrow pockets are dangerous because placement tools fill them with cells whose routes cannot escape. A beautiful row of macros can still be poor if all pins face one congested corridor. Trial placement and global routing are the quickest reality check.
Memory-dominated chips often use repeated tiles. Tiling localizes bandwidth, regularizes timing, and makes verification scalable. Yet strict repetition may conflict with global networks or package bumps. Floorplans should preserve modularity where it improves closure while allowing controlled asymmetry near edges, controllers, and shared resources.
**Connectivity should follow data movement, not just logical hierarchy.** RTL modules reflect ownership and verification boundaries, but a physical block may communicate more with a neighboring module than with its logical parent. Register-transfer bandwidth, latency sensitivity, fanout, and traffic direction provide better placement weights. Wide interfaces deserve short, direct corridors; low-rate control can tolerate longer paths. Crossing a die costs energy and timing even when synthesis reports the same logical function.
Estimated wire delay grows with distributed resistance and capacitance. Buffer insertion changes the scaling, but it consumes power and area and creates more endpoints for variation. Early timing uses virtual routes and estimated parasitics; after placement, extraction provides sharper evidence. If critical paths repeatedly span the floorplan, the right fix may be pipelining or partitioning rather than heroic physical optimization.
**Power planning starts before detailed placement.** Rings, meshes, straps, rails, vias, bumps, and package planes form one impedance network. Grid pitch and width are chosen from current density, voltage-drop limits, electromigration, available routing layers, and bump locations. Macros need explicit power access; narrow channels must not become both signal highways and the only power entrance.
Static voltage drop is approximately governed by (V=IR), while fast load steps also excite inductive and capacitive behavior. Vectorless estimates identify broad weaknesses, and activity-based analysis finds workload hotspots. Decoupling capacitance is placed near changing loads but competes for leakage and area. Reinforcing the grid late can block signal routing, so early floorplans reserve the necessary metal and via farms.
Multiple voltage domains introduce boundaries, isolation cells, level shifters, retention cells, separate grids, and power switches. Their physical placement must match the power-state architecture. A level shifter placed far from the domain boundary adds delay and creates illegal routing across shutoff regions. Power switches require distributed area and control sequencing; clustering them merely to simplify the diagram may cause local droop.
**I/O placement couples silicon to the package and board.** Wire-bond pads usually live at the perimeter, while flip-chip bumps can distribute power and signals over the die. High-speed PHYs want short, matched connections to package balls and controlled proximity to reference clocks. Memory interfaces may require prescribed byte-lane geometry. ESD devices, keepouts, seal structures, and analog supply separation consume edge resources.
Package co-design prevents a locally convenient bump map from producing impossible substrate escape. Power bumps should align with current demand, not just a uniform aesthetic. Signal bumps need return-current paths. In chiplet systems, die-to-die edges, interposer routing, bridge locations, and shared thermal interfaces make package geometry a first-class floorplan constraint.
**Congestion is demand exceeding routing supply.** Demand comes from pin density, net topology, buffering, scan chains, clocks, and detours around blockages. Supply comes from track count, usable layers, preferred directions, design rules, and obstacles. Global-routing heat maps show overflow by region and layer. The remedy may be lower utilization, macro movement, channel widening, pin reassignment, cell spreading, synthesis restructuring, or access to more layers.
Pin access is especially important at advanced nodes because restrictive patterning and complex design rules make nominal empty space unusable. A region can show moderate global congestion yet fail detailed routing at dense standard-cell or macro pins. Technology-aware placement, cell padding, alternate cell architectures, and local blockages reduce this risk.
Scan-chain reorder and physical synthesis should operate after placement information exists. A purely logical scan order can snake across the die and waste routing. High-fanout controls require buffering regions. Spare cells should be distributed so later engineering changes have nearby logic options rather than a remote cluster that cannot meet timing.
**Clock planning shapes both timing and power.** Clock roots, generated clocks, gating cells, macro clock pins, and balancing regions should be visible in the floorplan. A conventional tree minimizes skew through branching buffers; a mesh improves robustness at substantial capacitance and power. Large obstacles distort both. Useful skew can improve setup timing but must remain safe for hold timing across corners.
Clock-domain crossings do not disappear when domains are adjacent, but distance affects synchronizer routing and shared control. PLLs and oscillators need noise isolation, clean supplies, and practical clock-distribution exits. Placing a PLL in a quiet corner is counterproductive if its clock must cross every noisy macro pin corridor.
**Thermal gradients are physical constraints.** Compute arrays, SerDes, regulator stages, and dense memories generate different heat densities. Clustering hot blocks creates a peak that increases leakage, slows transistors, accelerates wear, and raises cooling requirements. Spreading heat can help, but longer wires may increase power. Early compact thermal models and package boundary conditions make this tradeoff quantitative.
Temperature also changes timing and power-grid resistance. Modern nodes can show temperature inversion in some voltage regimes, so the slowest condition is not assumed from intuition. Thermal sensors should sample meaningful hotspots and be reachable by control logic. Throttling and workload migration are architectural partners to physical heat spreading.
**Analog and mixed-signal regions need explicit protection.** Guard rings, deep wells, substrate contacts, supply filters, and spacing reduce coupling from digital switching. Sensitive inputs avoid clock trunks and switch-mode power nodes. Matching structures require consistent orientation, surroundings, and stress. The floorplan reserves these conditions before digital tools consume the whitespace.
Verification evolves through progressively more realistic prototypes: area spreadsheet, connectivity sketch, macro placement, trial standard-cell placement, early clock plan, global route, extracted timing, power integrity, thermal analysis, and design-rule checks. Each loop should answer a risk question. Repeating place-and-route without recording what changed produces activity, not convergence.
**A floorplan is complete when downstream tools have room to succeed and the evidence supports that claim.** Its dimensions, macro topology, package interface, grid, domains, channels, clocks, and thermal strategy form one executable hypothesis. Preserve alternatives early, measure congestion and timing rather than guessing, and change architecture when geometry exposes a fundamental mismatch. The best floorplan is not the densest picture; it is the smallest credible foundation for predictable closure and robust silicon.