floorplanning basics

**Floorplanning** — the first step of physical design, defining the chip's spatial organization: die size, block placement, I/O ring, and power grid topology. **Key Decisions** - **Die Size**: Estimated from total gate count + memory + analog blocks + margins - **Aspect Ratio**: Width/height — affects routing congestion and package compatibility - **Block Placement**: Position major IP blocks (CPU cores, GPU, memory controllers, PHYs) to minimize wire length and meet timing - **I/O Ring**: Arrange I/O pads around chip perimeter matching package pin assignment - **Power Grid**: Define VDD/VSS grid structure — mesh width, strap density, ring size **Floorplanning Rules** - Place blocks with heavy communication close together - Place analog blocks away from noisy digital blocks - Ensure power grid meets IR drop targets everywhere - Reserve routing channels between blocks for signal and clock paths - Account for clock tree insertion (clock root location) **Hard vs Soft Macros** - Hard macro: Fixed layout (SRAM, PHY) — placed as-is - Soft macro: Synthesized logic — shape and size flexible during placement **Impact** A bad floorplan makes timing closure impossible regardless of how much effort is spent in placement and routing. Good floorplanning is 60% of physical design success.