GAA Nanosheet 2020s Confront Fin Pitch Wall FinFET Left Open

# Gate-All-Around / Nanosheet Transistors (2020s): Step 1 — Confront the Fin-Pitch Wall FinFET (2010s) Left Open

## 1. The Boundary This Series Picks Up

`finfet_2010s` closed with an explicit, deliberately unresolved boundary: bulk tri-gate FinFET had bought roughly a decade of continued scaling by restoring three-sided gate control over the channel, but that series' own Step 18 and Step 20 already identified that fin-pitch scaling was converging on hard limits by the 10nm generation. This step opens exactly where that series stopped, taking the convergence seriously rather than re-deriving it.

## 2. What, Specifically, Had Run Out

Three distinct pressures converged at once. First, fin width itself could not shrink much further without degrading channel mobility and drive current — a narrower fin means less silicon cross-section carrying current, and body-depletion effects (`finfet_2010s` Step 13) worsen as the fin thins. Second, fin-to-fin pitch could not tighten further without parasitic capacitance between adjacent gates rising faster than the density gain was worth. Third, fin-height and fin-width process variation (`finfet_2010s` Step 5), already a first-order concern at 14nm/10nm, scales worse, not better, as the fin's cross-section shrinks toward the same magnitude as the variation itself.

## 3. Why the Fix Is Not 'A Narrower Fin'

A natural first instinct is to keep pushing the same geometry thinner. That instinct runs directly into physics: FinFET's gate wraps three sides of the fin (top and two sidewalls), leaving the fin's bottom corner electrostatically weaker than the other three. Narrowing the fin to compensate for that weak corner eventually makes the whole fin too narrow to carry useful drive current at all, long before pitch or variation limits are even reached. The architecture's geometry, not just its dimensions, had reached a wall.

## 4. What This Step Does and Does Not Cover

This step only establishes the problem precisely, in the same deliberately narrow way `finfet_2010s` Step 1 confronted the planar wall before proposing a fix. The architectural answer — wrapping the gate around all four sides of a horizontal channel instead of three sides of a vertical fin — is this series' next step.

Where FinFET's Scaling Curve Actually Bent fin width, fin-to-fin pitch headroom, and process-variation-to-dimension ratio across the last FinFET generations fin width available before mobility/drive-current loss variation-to-dimension ratio (rising as fin cross-section shrinks) 10nm-class generation: the two curves cross fin width, pitch headroom, and variation control converged on the same generation, not independently this is the precise boundary finfet_2010s Step 18 identified and this series now addresses directly
Three Pressures, One Convergence Point the simultaneous limits that close out bulk tri-gate FinFET scaling NARROWING FIN WIDTH less silicon cross-section per fin means falling drive current and mobility as width shrinks TIGHTENING FIN PITCH closer fins raise gate-to-gate parasitic capacitance faster than density gain justifies WORSENING VARIATION fin height/width process variation does not shrink as fast as the fin itself does a geometry problem, not a dimension problem — the next step's fix changes the gate wrap itself

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