gate all around nanosheet width
**Nanosheet Width Optimization** is the **critical design parameter in gate-all-around (GAA) transistors that controls the effective drive current, parasitic capacitance, and electrostatic behavior by setting the physical width of each silicon nanosheet channel** — replacing the fin width as the primary device sizing knob. Unlike FinFETs where drive current is quantized by adding fins, GAA nanosheets allow continuous width tuning within process limits, enabling more precise performance/power optimization for each cell in a standard cell library.
**Nanosheet Width as Device Sizing**
- **FinFET sizing**: Current ∝ number of fins (integer steps) → coarse granularity (1x, 2x, 3x fin).
- **Nanosheet sizing**: Current ∝ nanosheet width (Wns) × number of stacked sheets → finer granularity.
- Typical width range: 8–70 nm per sheet, with minimum pitch set by lithography.
- Sheet count: 2–5 per stack (3 is most common at 3nm).
**Drive Current vs. Nanosheet Width**
- Ion ∝ Wns (linear) — wider sheets → more channel area → more current per stack.
- But parasitics also scale: Cgg, Cgd, junction capacitance all increase with Wns.
- Design sweet spot: Wns that maximizes Ion/Cgg (intrinsic frequency performance).
**NMOS vs. PMOS Width Optimization**
| Parameter | NMOS Nanosheet | PMOS Nanosheet |
|-----------|---------------|---------------|
| Channel material | Si | SiGe or Ge |
| Optimal Wns | Narrower (less junction cap) | Wider (compensate lower hole µ) |
| Mobility enhancement | Tensile stress in Si | Compressive strain in SiGe |
| Drive current ratio NMOS/PMOS | ~1.8–2× (Si vs. SiGe-p) | Compensated by width tuning |
**Width Optimization for Standard Cell Design**
- Standard cells (inverter, NAND, NOR) target NMOS/PMOS current balance → different Wns for N vs. P.
- At 3nm (Samsung SF3): NMOS uses 3 × Si sheets; PMOS uses 3 × SiGe sheets with wider Wns or different Ge%.
- Separate NMOS/PMOS sheet definition enabled by CMOS GAA integration flow: grow Si/SiGe superlattice for NMOS, SiGe/Si for PMOS (or mix-and-match channels).
**Electrostatics vs. Width**
- Shorter sheet width → better electrostatic control (gate wraps more completely → less fringe field from S/D).
- Wider sheet → drain-induced barrier lowering (DIBL) increases slightly.
- Minimum sheet width set by short-channel control spec (DIBL < 50–100 mV/V), not just lithography.
**Process Constraints on Nanosheet Width**
- **Maximum width**: Limited by nanosheet release etch — very wide sheets sag without support → structural failure.
- **Minimum width**: Limited by lithography (EUV patterning minimum), contact resistance (too narrow → current crowding).
- **Sheet-to-sheet variation**: Epitaxial thickness variation → each sheet slightly different width → VT variation → σVT increases.
**Width Tuning for Low-Power vs. High-Performance**
| Application | Nanosheet Width Strategy | Outcome |
|------------|------------------------|--------|
| HP (high performance) | Max width, max sheet count | Highest Ion, highest Cgg |
| LP (low power) | Narrow width, fewer sheets | Lowest Cgg, lowest IOFF |
| HPC | Full-width NMOS + wide SiGe PMOS | Balanced drive, lower leakage |
| SRAM | Minimum width for NMOS pull-down | Small cell area, tight β ratio |
**Industry Implementations**
- **Samsung SF3 (3nm GAA)**: 3 Si nanosheets, Wns ~20–40 nm, sheet thickness 4–5 nm.
- **TSMC N2 (2nm)**: Nanosheet GAA replacing FinFET; Wns details proprietary but similar range.
- **Intel 20A/18A**: RibbonFET (nanosheet variant); width tuning cited as key performance lever.
Nanosheet width optimization is **the central lever for achieving performance-power targets in GAA transistor design** — by providing a continuous, analog-like control over drive current and capacitance that FinFET's discrete fin count could not match, nanosheet width tuning enables circuit designers and process engineers to collaborate at a new level of precision in defining what each logic standard cell delivers at 3nm and beyond.