gate cut

**Gate Cut and Diffusion Break** are **patterning techniques that physically isolate adjacent transistors by cutting continuous gate lines and fin/diffusion structures** — replacing the traditional shallow trench isolation (STI) approach at advanced nodes where FinFET and GAA architectures use continuous fin arrays that must be selectively broken to define individual device boundaries. **Why Gate Cut/Diffusion Break?** - In FinFET/GAA architectures, fins are patterned as continuous parallel lines across the entire cell row. - Transistors are defined by selectively removing (cutting) gates and fins where isolation is needed. - Traditional STI isolation between devices would require wide gaps — gate cut enables tighter packing. **Types of Diffusion Break** **Single Diffusion Break (SDB)**: - One fin pitch of space between adjacent cells. - Fin is cut (removed) in the isolation region, and a dummy gate sits over the cut. - Saves ~20-30% cell width compared to double diffusion break. - Used at 5nm and below for high-density standard cells. **Double Diffusion Break (DDB)**: - Two fin pitches of space between adjacent cells. - Provides better electrical isolation and more process margin. - Used at 7nm and above, or for cells requiring strong isolation. **Gate Cut Process** 1. **Continuous gates** patterned across the entire cell row. 2. **Gate cut mask**: Defines where gates must be severed. 3. **Cut etch**: Removes gate material in the cut region. 4. **Dielectric fill**: Fills the cut with SiN or oxide for isolation. **Process Integration Challenges** - **Cut placement**: Must be precisely aligned to gate and fin patterns — overlay error < 2 nm. - **Cut-before-gate vs. Cut-after-gate**: - Cut-before: Easier integration but limits metal gate fill options. - Cut-after: Better gate quality but requires etching through metal gate stack. - **EUV patterning**: Gate cut layers are among the first to adopt EUV — tight pitch and placement accuracy demands. **Impact on Standard Cell Design** - SDB enables 6-track and 5-track standard cell heights — increasing logic density. - Design rules must account for cut-to-gate spacing, cut-to-fin spacing. - EDA tools optimize cut placement during place-and-route. Gate cut and diffusion break are **essential patterning innovations for advanced FinFET and GAA processes** — they enable the dense transistor packing required at 5nm and below by replacing bulk isolation with surgical removal of specific gate and fin segments.