Gate-Leakage

Gate leakage is current flowing through a transistor’s gate-insulating structure. In an ideal MOS picture, the dielectric blocks steady conduction between the gate and semiconductor. Real films allow small currents, and sufficiently thin insulating barriers permit quantum-mechanical tunneling. This current path is different from subthreshold current flowing from source to drain through the channel.

Thinning the dielectric changes both control and leakage. A thinner gate dielectric can increase gate capacitance and improve electrostatic control, but it also reduces the barrier width available to suppress tunneling. The resulting trade-off helped make simple silicon-dioxide thinning increasingly difficult. Physical thickness and material properties must both be specified when comparing leakage measurements.

Gate leakage Conceptual comparison; not a manufacturing specification or scale drawing Gate path Gate → dielectric → silicon Tunneling or defect transport Channel path Source → channel → drain Subthreshold conduction Comparison basis Bias + area + temperature Identify mechanism first Gate leakage and subthreshold leakage follow different paths and require different diagnoses.

IBM’s 1999 modeling work connects several ultrathin-oxide effects. The published study treats quantization, polysilicon depletion, and direct tunneling in MOSFETs. These effects change the relation between applied voltage, stored charge, and current. A classical geometric capacitor model alone cannot explain every observation in such a thin gate stack.

A measured gate current needs a stated electrical configuration. Record which terminal is biased, the voltage polarity and magnitude, the temperature, and whether current is reported per device or per unit area. Otherwise two values can look inconsistent simply because they describe different operating conditions. Defect-assisted leakage also should not be casually identified as direct tunneling.

Reducing gate leakage does not eliminate all standby power. Channel leakage, junction currents, and circuit-level paths remain possible. A process change that improves the gate dielectric therefore needs separate assessment of the other mechanisms. The useful design question is how the complete device and circuit meet their operating and standby requirements.

Sources and further reading. [IBM quantum-mechanical MOSFET modeling, 1999](https://research.ibm.com/publications/modeling-and-characterization-of-quantization-polysilicon-depletion-and-direct-tunneling-effects-in-mosfets-with-ultrathin-oxides); [Chenming Hu, scaling and leakage](https://www.chu.berkeley.edu/wp-content/uploads/2020/01/Chenming-Hu_ch7.pdf).

Read Gate leakage as nonideal current across the gate-insulating structure, measured under a defined bias and separated from channel leakage.

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