Glitch Free Clock Mux

A glitch-free clock multiplexer is what a chip needs whenever it switches between two clock sources that are not already synchronized to each other — a plain combinational multiplexer, the kind that works perfectly well for ordinary data signals, can produce a brief, extra pulse right at the moment of switching if the select signal changes while one of the clock inputs happens to be mid-transition, and on a clock line, even a single glitch that extra pulse is itself a clock edge the rest of the chip was never supposed to see.

The failure mode is specific to clocks because every other signal in a digital design is read at a controlled sampling instant, while a clock is itself the thing that defines when sampling happens. An ordinary data signal passing through a combinational multiplexer can glitch briefly during a select change, and downstream logic simply ignores that transient because it is only sampled on the next clock edge, well after any switching transient has settled. A clock signal has no equivalent protection — every edge on a clock line is, by definition, a sampling instant for whatever flip-flops it drives, so a spurious extra edge or a runt pulse crossing the switching threshold is read by downstream logic exactly as if it were a legitimate clock tick, potentially capturing incorrect data or, worse, violating setup and hold timing in a way that drives part of the circuit into a metastable state.

The standard glitch-free design avoids the entire problem by restructuring when the switch is permitted to happen, rather than trying to filter out a glitch after it occurs. A typical glitch-free clock mux uses two cascaded latches per clock input, gated so that the select signal is only allowed to take effect while the currently active clock is at its low phase — the switch is synchronized to each clock's own low-to-high transition rather than happening asynchronously whenever the select signal itself changes. This structural guarantee means the multiplexer's output can only ever be low at the moment a switch actually occurs, so the new clock's first rising edge after the switch is a clean, full-width edge rather than a partial or extra pulse — the circuit makes a glitch structurally impossible rather than detecting and suppressing one.

This is structurally the same discipline this series has already covered for metastability-safe clock domain crossing, applied one level up to the clock network itself rather than to data crossing between domains. A clock domain crossing synchronizer defers an asynchronous signal until a known-safe clock edge before letting the rest of the circuit act on it; a glitch-free clock mux defers an asynchronous select request until a known-safe phase of the currently active clock before letting the switch actually happen. Both techniques share the same underlying insight — an arbitrary, asynchronous event cannot be allowed to act on a synchronous system at an arbitrary moment, so the system is restructured to only ever respond to that event at a moment it has already proven safe.

This circuit shows up in several places a modern chip actually needs to change which clock is driving a region of logic. Clock gating for power management turns a clock off to an idle block to save power and must turn it back on cleanly without a glitch when that block wakes up. Switching between a primary clock source and a backup, or between a PLL's reference clock and a bypass path during startup or a fault condition, both require exactly this kind of clean handoff, since a glitch injected during a clock-source failover is precisely the moment a chip is already under the most stress and least able to tolerate an unpredictable extra edge. Any system with more than one clock source feeding the same logic, which describes essentially every modern SoC with power domains and multiple PLLs, needs this circuit somewhere in its clock tree.

A glitch-free clock multiplexer is a reminder that a clock signal is not just another wire carrying a square wave — it is the reference every other signal in its domain is measured against, which means the usual rules for switching a signal cleanly do not apply to it. The circuit earns its complexity, relative to an ordinary mux, specifically because the thing it switches is the clock that decides when every downstream glitch would or would not matter.