globally asynchronous locally synchronous

**Globally asynchronous locally synchronous (GALS)** is the **architecture pattern where each subsystem runs with its own local clock while inter-domain communication uses asynchronous interfaces** - it combines synchronous design productivity with scalable multi-domain integration. **What Is GALS?** - **Definition**: Partitioning a chip into locally clocked islands connected by asynchronous or pausible-clock links. - **Local Advantage**: Each domain can optimize frequency, voltage, and clock tree independently. - **Global Interface**: Cross-domain boundaries use synchronizers, FIFOs, or handshake wrappers. - **Target Systems**: Large SoCs with heterogeneous accelerators and variable workload behavior. **Why GALS Matters** - **Scalability**: Reduces global clock closure complexity in very large designs. - **Power Efficiency**: Domains can run at right-sized frequency and voltage without full-chip penalties. - **Variation Isolation**: Timing issues in one island do not force global frequency reduction. - **IP Reuse**: Independent clock domains simplify integration of third-party or legacy blocks. - **Robustness**: Better tolerance to local process and thermal differences across the die. **How GALS Is Realized** - **Domain Partitioning**: Group logic by latency needs, workload profile, and voltage targets. - **Boundary Design**: Insert CDC-safe interfaces with verified buffering and metastability protection. - **System Validation**: Stress asynchronous crossings with jitter, drift, and burst-traffic scenarios. GALS is **a pragmatic architecture for modern heterogeneous SoCs where one global clock is no longer optimal** - it preserves synchronous design strengths while enabling flexible, variation-aware system scaling.