graphics memory

GDDR and LPDDR are the two mass-market high-performance flavors of DRAM, and they exist because bandwidth and power pull in opposite directions. Every modern system needs working memory, but a gaming GPU, a smartphone, a server CPU, and an AI training accelerator want wildly different things from it — raw throughput, energy per bit, sheer capacity, or bandwidth per watt. Rather than one compromise part, the industry ships several specialized standards built on the same underlying DRAM cell: standard DDR for CPUs, GDDR for graphics, LPDDR for battery-powered devices, and HBM for accelerators. Understanding the family means understanding which single metric each variant was willing to sacrifice everything else for.\n\n**All these memories share the same DRAM cell; what differs is the interface tuned to a target.** The storage element is identical everywhere — a one-transistor, one-capacitor cell that leaks and must be refreshed. What the DDR, GDDR, LPDDR, and HBM standards actually specify is everything *around* the cell array: the signaling scheme, the bus width, the operating voltage, the packaging, and how channels are organized. So the real engineering contest happens at the physical interface (the PHY), not in the bit cell. Standard DDR optimizes for capacity and field-upgradable DIMM modules; the other three each specialize hard in one direction.\n\n**GDDR maximizes raw bandwidth per pin for GPUs, accepting higher power and soldered-down placement.** GDDR6, GDDR6X, and GDDR7 push per-pin data rates to the limit — roughly 16, 21, and 32 gigabits per second respectively — by soldering the chips point-to-point right next to the GPU, running wide aggregate buses (256 to 384 bits), and adopting multi-level signaling (GDDR6X's PAM4, GDDR7's PAM3) that sends more than one bit per symbol. The single priority is feeding thousands of shader cores; power draw and total capacity are secondary. That is exactly why graphics cards use GDDR rather than the DIMMs a CPU uses.\n\n**LPDDR minimizes energy per bit for battery devices, trading peak bandwidth and upgradability for low power.** LPDDR5 and LPDDR5X run lower voltages, add aggressive power-saving modes (deep sleep, partial-array self-refresh, low-swing I/O), and ship as compact package-on-package or soldered parts sitting on top of or beside the SoC. Per-pin rates are respectable — LPDDR5X reaches about 8.5 Gbps — and wide buses give strong aggregate bandwidth, but the metric that governs every design choice is picojoules per bit and standby power. Once confined to phones, LPDDR now fills laptops, AI edge devices, and even datacenter inference nodes where energy, not capacity, is the binding constraint.\n\n**HBM sits above both: 3D-stacked dies on a silicon interposer give the widest bus and best bandwidth-per-watt, at the highest cost.** High-bandwidth memory stacks DRAM dies vertically with through-silicon vias and places them on a silicon interposer beside the processor, exposing an enormous 1024-bit-per-stack bus at modest per-pin speeds. That width plus short interposer traces yields the best bandwidth per watt of any option — ideal for AI training accelerators — but the packaging is expensive and per-stack capacity is limited. GDDR is the cheaper way to buy bandwidth; HBM is the premium one.\n\n| Memory | Optimized for | Where it lives | Typical per-pin rate | Packaging |\n|---|---|---|---|---|\n| DDR5 | Capacity, upgradability | CPU / server main memory | ~4.8–8 Gbps | DIMM modules |\n| GDDR6 / 6X / 7 | Raw bandwidth per pin | Gaming & pro GPUs | ~16 / 21 / 32 Gbps | Soldered, point-to-point |\n| LPDDR5 / 5X | Energy per bit | Phones, laptops, AI edge | ~6.4 / 8.5 Gbps | PoP / soldered near SoC |\n| HBM3 / 3E | Bandwidth per watt | AI training accelerators | ~6.4 Gbps × 1024-wide bus | 3D stack on interposer |\n\n```svg\n\n```\n\nThe unhelpful way to read GDDR and LPDDR is as two arbitrary DRAM brand names, or worse, as a fast one and a slow one. The useful way is to see a single DRAM cell wrapped in four different interfaces, each of which threw away three metrics to win a fourth: DDR keeps capacity and upgradable modules, GDDR chases raw bandwidth per pin for GPUs, LPDDR chases energy per bit for anything on a battery, and HBM chases bandwidth per watt by stacking dies on an interposer. AI has since redrawn the map — training reaches for HBM, power-bound inference reaches for LPDDR, and GDDR holds the cost-sensitive middle. Read the DRAM family through a which-metric-did-it-sacrifice-everything-for lens rather than a faster-versus-slower lens, and the multi-level signaling, the package-on-package, the silicon interposer, and the soldered-down GPU memory stop looking like unrelated specs and resolve into one idea: the cell is fixed, so you engineer the interface to the job.