ground bounce
**Ground bounce** (also called **ground noise** or **simultaneous switching output noise on ground**) is the **transient voltage fluctuation on the ground (VSS) network** caused by large, rapid changes in current flowing through the parasitic inductance of ground connections — particularly package bond wires, bumps, or pins.
**How Ground Bounce Occurs**
- When digital outputs switch from high to low, they discharge load capacitance through the ground path.
- If many outputs switch simultaneously, the aggregate current change ($dI/dt$) through the ground path inductance ($L$) creates a voltage: $V_{bounce} = L \cdot \frac{dI}{dt}$.
- This voltage appears as a **temporary rise** in the local ground level — the chip's internal ground is momentarily "bounced" above the true external ground.
**Why Ground Bounce Is a Problem**
- **False Switching**: If the ground bounces high enough, a non-switching output that is supposed to be LOW may appear HIGH to the receiving circuit. Similarly, an input buffer may see a valid LOW as HIGH.
- **Noise Margin Erosion**: Ground bounce reduces the effective noise margin for all signals referenced to the bouncing ground.
- **Setup/Hold Violations**: Ground bounce on clock or data paths causes effective timing jitter — shifting edges and violating timing constraints.
- **Analog/Mixed-Signal Impact**: Sensitive analog circuits (ADCs, PLLs, sense amplifiers) are especially vulnerable — even millivolts of ground bounce can cause errors.
**Factors Affecting Ground Bounce**
- **Number of Simultaneously Switching Outputs (SSO)**: More outputs switching at the same time → larger $dI/dt$.
- **Load Capacitance**: Larger load capacitance → more charge to discharge → more current.
- **Switching Speed**: Faster edge rates → higher $dI/dt$ → worse bounce.
- **Package Inductance**: Higher inductance (longer bond wires, fewer ground pins) → worse bounce.
- **Driver Strength**: Stronger drivers deliver more current → larger $dI/dt$.
**Mitigation Strategies**
- **More Ground Pins/Bumps**: Reduce the effective inductance by using more parallel ground connections.
- **Staggered Switching**: Avoid all outputs switching simultaneously by using skewed clock domains or staggered enable timing.
- **Reduced Drive Strength**: Use the minimum drive strength needed — slower edges reduce $dI/dt$.
- **Decoupling Capacitors**: On-die and in-package decaps absorb transient current, reducing the current through the inductance.
- **Separate Power Domains**: Isolate noisy I/O ground from sensitive analog or core ground.
- **Controlled Impedance**: Match output impedance to transmission line impedance to reduce reflections and ringing.
Ground bounce is a **primary signal integrity concern** in IC design — managing it requires coordinated effort between I/O design, package design, and PCB layout.