grounded-gate nmos
**Grounded-gate NMOS (GGNMOS)** is the **most widely used ESD protection clamp in CMOS technology, leveraging the parasitic lateral NPN bipolar transistor inherent in every NMOS device** — providing robust, high-current ESD discharge capability by operating in avalanche-triggered snapback mode with the gate tied to ground (source).
**What Is GGNMOS?**
- **Definition**: An NMOS transistor with its gate connected to its source (ground), designed to operate as an ESD clamp by exploiting the parasitic bipolar junction transistor (BJT) formed by the drain (collector), body (base), and source (emitter) regions.
- **Normal Operation**: With gate at ground, the MOSFET is off and draws negligible leakage current — the device is invisible to normal circuit operation.
- **ESD Activation**: When drain voltage rises to the avalanche breakdown point, impact ionization generates electron-hole pairs. Holes flow to the grounded body, raising the body potential and forward-biasing the base-emitter junction of the parasitic NPN BJT.
- **Snapback**: Once the parasitic BJT turns on, the device enters snapback — voltage drops to Vh while current increases dramatically, providing a low-impedance discharge path.
**Why GGNMOS Matters**
- **Universality**: Available in every CMOS technology without any additional process steps — foundries provide GGNMOS ESD device models as standard PDK components.
- **High Current Capacity**: A well-designed GGNMOS can handle 5-10 mA/µm of device width, meaning a 500 µm wide device handles 2.5-5 A of ESD current.
- **Established Design Knowledge**: Decades of characterization data and design guidelines exist for GGNMOS across all technology nodes from 350nm to 3nm.
- **Latchup Safety**: Unlike SCRs, GGNMOS has relatively high holding voltage (3-5V), providing natural latchup immunity for most operating voltages.
- **Process Portability**: GGNMOS designs port across technology nodes with well-understood scaling rules.
**GGNMOS Operation Mechanism**
**Phase 1 — Off State (Normal Operation)**:
- Gate = Source = Ground. MOSFET channel is off.
- Only sub-threshold leakage flows (pA to nA range).
**Phase 2 — Avalanche Initiation (ESD Arrives)**:
- Drain voltage rises rapidly during ESD event.
- At the drain-body junction, high electric field causes impact ionization.
- Generated holes flow through the body resistance to the grounded body contact.
**Phase 3 — BJT Turn-On (Snapback)**:
- Hole current through body resistance (Rsub) raises the body potential.
- When Vbody > 0.7V, the source-body junction forward biases.
- The parasitic NPN (drain-body-source) turns on with high current gain.
- Device voltage "snaps back" from Vt1 to Vh.
**Phase 4 — Sustained Clamping**:
- Device operates in low-impedance BJT mode, conducting amperes of ESD current.
- Voltage remains at Vh + I × Ron until the ESD pulse decays.
**Key Design Parameters**
| Parameter | Typical Range | Design Knob |
|-----------|--------------|-------------|
| Trigger Voltage (Vt1) | 6-12V | Channel length, drain implant |
| Holding Voltage (Vh) | 3-5V | Ballast resistance, silicide block |
| It2 (Failure Current) | 5-10 mA/µm | Device width, contacts, metal |
| Turn-On Time | 200-500 ps | Layout parasitics |
| Leakage | < 1 nA | Gate bias, channel length |
**Layout Design Rules**
- **Silicide Block**: Non-silicided drain region adds ballast resistance, improving current uniformity and raising Vh to prevent latchup.
- **Multi-Finger Layout**: Use many parallel fingers (10-50) with shared source/drain contacts for uniform current distribution.
- **Substrate Contacts**: Dense body/substrate contacts between fingers to control body potential and ensure uniform triggering.
- **Metal Width**: Wide metal connections (M1 through top metal) to handle peak ESD current without electromigration or metal fusing.
- **Guard Rings**: P+ guard rings around the device to collect substrate current and prevent latchup in adjacent circuits.
GGNMOS is **the workhorse of CMOS ESD protection** — by cleverly repurposing the parasitic bipolar transistor that exists in every NMOS device, designers get a robust, well-characterized, and area-efficient ESD clamp that has protected billions of chips across four decades of CMOS technology.