metal gate integration
**Metal Gate Integration** is the **process of forming dual work-function metal gate stacks for NMOS and PMOS transistors in a replacement-metal-gate (RMG) flow** — where multiple ultra-thin metal layers are deposited into nanometer-scale gate trenches to set the transistor threshold voltage, requiring atomic-level thickness control and complex multi-layer ALD sequences that are among the most challenging integration steps in sub-14nm CMOS.
**Why Metal Gates?**
- **Poly-Si gates** (legacy): Fermi-level pinning with high-k dielectrics, poly depletion effect → high equivalent EOT.
- **Metal gates**: No poly depletion, work function set by metal composition → lower EOT, higher performance.
- Transition occurred at 45nm node (Intel 2007) → industry standard since 32nm.
**Replacement Metal Gate (RMG) Flow**
1. **Dummy gate**: Form transistor with sacrificial poly-Si gate.
2. **ILD deposition + CMP**: Deposit interlayer dielectric, polish to expose dummy gate top.
3. **Dummy gate removal**: Wet etch (TMAH) removes poly-Si — leaves gate trench.
4. **High-k deposition**: ALD HfO2 (~1.5-2 nm) — gate dielectric.
5. **Work function metals**: ALD multi-layer metal stack — sets NMOS and PMOS Vt.
6. **Gate fill**: CVD W or other low-resistance metal fills the remaining gate trench.
7. **Gate CMP**: Polish back excess metal — isolate individual gates.
**Work Function Engineering**
| Transistor | Target Work Function | Metal Stack | Vt Range |
|-----------|---------------------|------------|----------|
| NMOS | ~4.1-4.3 eV | TiAl, TaAl (n-type WFM) | 0.2-0.5 V |
| PMOS | ~4.8-5.0 eV | TiN, TaN (p-type WFM) | -0.2 to -0.5 V |
- **Multi-Vt flavors**: Different metal layer thicknesses create eHVT, HVT, SVT, LVT, eLVT.
- Each Vt option requires selective patterning to add/remove metal layers in specific transistor regions.
- 5+ Vt options at advanced nodes → 5+ additional litho-etch steps in the gate module.
**Gate Stack Complexity**
- Total gate stack (from channel up): Interface layer (SiO2, ~0.5 nm) → High-k (HfO2, ~1.5 nm) → Barrier (TiN, ~1 nm) → P-WFM → N-WFM → Barrier → W fill.
- Total metal thickness in gate: 5-15 nm — must fit inside gate trench (< 20 nm at 5nm node).
- **Gate trench fill challenge**: At 3nm GAA, gate wraps around 3-4 nanosheets with ~8 nm spacing → metal must fill incredibly tight spaces.
**ALD Requirements**
- Every metal layer deposited by ALD for atomic-level thickness control.
- Thickness uniformity: < 0.5 Å variation across wafer.
- Composition control: TiAl ratio determines work function — ±0.5% composition variation → ±10 mV Vt shift.
Metal gate integration is **arguably the most complex module in advanced CMOS manufacturing** — the requirement to deposit 5-10 distinct ultra-thin metal layers inside nanometer-scale trenches with atomic-level precision, while engineering different work functions for NMOS/PMOS across multiple Vt flavors, represents the pinnacle of semiconductor process engineering.