metal gate cmos

**High-k/Metal Gate (HKMG) Process** is the **CMOS gate stack technology that replaced polysilicon/SiO₂ gates with hafnium-based high-k dielectrics and metal gate electrodes — solving the gate leakage crisis that made sub-2nm SiO₂ gates physically impossible by providing much higher capacitance per unit area at a given physical thickness, while eliminating the polysilicon depletion effect that degraded effective oxide thickness, first deployed at the 45nm node and remaining the foundation of every advanced CMOS gate stack through GAA nanosheets**. **The SiO₂ Scaling Limit** MOSFET drive current ∝ gate capacitance ∝ ε/t_ox. As technology scaled, SiO₂ gate dielectric was thinned to increase capacitance. At 1.2nm thickness (~5 atomic layers), direct quantum mechanical tunneling caused gate leakage current of 100 A/cm² — unacceptable for both power consumption and reliability. The solution: replace SiO₂ (k=3.9) with a higher-k material that provides the same capacitance at a physically thicker (lower leakage) film. **The High-k Dielectric** HfO₂ (k ≈ 20) deposited by ALD to ~1.5-2.0nm physical thickness provides equivalent capacitance to ~0.4-0.5nm of SiO₂ (quantified as EOT — Equivalent Oxide Thickness). A ~0.5nm SiO₂ interfacial layer (IL) between the silicon channel and HfO₂ is retained for interface quality — total EOT of ~0.8-1.0nm with manageable gate leakage. **Why Metal Gates** Polysilicon gates have a depletion region (~0.3-0.4nm of additional EOT) that effectively increases the electrical thickness. Metal gates have no depletion — the gate capacitance is purely the physical dielectric. Additionally, the polysilicon/HfO₂ interface has Fermi level pinning that prevents proper threshold voltage setting. Metal gates solve both problems. **Replacement Metal Gate (RMG) Process** 1. **Dummy Gate Formation**: A sacrificial polysilicon gate is patterned over a thin SiO₂ layer during the front-end process flow. Source/drain implants and epitaxy are performed with the dummy gate in place. 2. **ILD Deposition and CMP**: Interlayer dielectric is deposited and planarized to expose the dummy gate top. 3. **Dummy Gate Removal**: Selective wet etch removes the polysilicon (NH₄OH or TMAH) and the underlying SiO₂, creating a gate trench. 4. **IL/High-k Deposition**: Thin SiO₂ interfacial layer (~0.5nm) grown by chemical oxide. ALD deposits HfO₂ (~1.5-2.0nm) conformally on the trench surfaces. 5. **Work Function Metal Stack**: Multiple ALD layers of TiN, TaN, TiAl, and TiAlC set the threshold voltage. For NMOS, a thicker TiAl layer shifts the work function toward the conduction band. For PMOS, TiN dominates, shifting toward the valliable band. 6. **Gate Fill**: Tungsten or aluminum fills the remaining trench volume to provide low-resistance gate connection. 7. **CMP**: Excess metal is removed by CMP, leaving metal only in the gate trench. **Multi-Vt Engineering** Modern SoCs require 4-6 different threshold voltage variants (SVT, LVT, ULVT, HVT, etc.) for power-performance optimization. These are achieved by varying the work function metal stack thickness (adding or removing TiN layers) — a key differentiator between foundries. High-k/Metal Gate is **the gate stack revolution that saved Moore's Law from the gate leakage wall** — replacing the simple polysilicon/SiO₂ structure that had served for 40 years with an atomically-engineered multilayer stack where each sub-nanometer layer of metal precisely tunes the most fundamental transistor parameter.