hkmg gate

**High-k/Metal Gate (HKMG) Last Integration** is **the replacement metal gate (RMG) process scheme in which a sacrificial polysilicon gate is used during front-end processing and subsequently removed after source/drain formation and ILD planarization, with the resulting cavity filled by high-k dielectric and metal gate electrode materials** — enabling the use of thermally sensitive work-function metals that cannot survive the high-temperature source/drain activation anneal in gate-first approaches. - **Gate-Last Rationale**: High-k dielectrics such as HfO2 interact with polysilicon at temperatures above 600 degrees Celsius, causing Fermi-level pinning and threshold voltage instability; by deferring metal gate deposition until after all high-temperature steps are complete, the gate-last scheme avoids these degradation mechanisms and provides wider work-function engineering flexibility. - **Sacrificial Gate Formation**: A dummy polysilicon gate is patterned on a thin interfacial oxide and high-k dielectric (or on a sacrificial oxide); standard spacer, LDD, halo, and source/drain processing follows as if the dummy gate were the final gate. - **ILD Planarization**: After source/drain silicidation and ILD deposition, CMP planarizes the surface to expose the top of the dummy polysilicon gate; the polish must stop precisely at the gate top without dishing into the surrounding ILD. - **Dummy Gate Removal**: Selective wet etch using ammonium hydroxide or TMAH removes the polysilicon, followed by dilute HF to strip the sacrificial oxide, leaving a high-aspect-ratio gate trench bounded by spacers on the sides and high-k dielectric or the channel at the bottom. - **High-k Deposition**: Atomic layer deposition (ALD) conformally deposits 1-2 nm of HfO2 or HfZrO2 at 250-300 degrees Celsius inside the gate trench; interface engineering using a thin SiO2 interlayer of 0.5-1.0 nm grown by chemical oxide or ozone-based methods controls interface state density and carrier scattering. - **Work-Function Metal Stack**: For NMOS, metals such as TiAl or TiAlC with work functions near 4.1 eV are deposited; for PMOS, TiN layers with work functions near 4.9 eV are used; the multi-layer stack may include barrier layers, wetting layers, and capping layers, all deposited by ALD or PVD with angstrom-level precision. - **Gate Fill**: After work-function metal deposition, the remaining trench volume is filled with low-resistivity tungsten or cobalt using CVD, followed by CMP to remove overburden and create a planar gate surface aligned with the ILD top. - **Threshold Voltage Tuning**: Multiple threshold voltage (Vt) flavors are achieved by varying the number and thickness of work-function metal layers through selective deposition and etch-back sequences, enabling standard-Vt, low-Vt, and high-Vt devices on the same chip. The HKMG gate-last scheme is the industry standard for advanced logic technologies because it decouples thermal budget constraints from gate material selection, enabling optimal transistor performance and reliability.