gate last process

**Replacement Metal Gate (RMG) / Gate-Last Process** is a **CMOS fabrication flow where a sacrificial polysilicon gate is used as a placeholder throughout most of the process, then replaced with the final high-k dielectric and metal gate** — enabling superior high-k/metal gate quality that cannot survive high-temperature source/drain processing. **Why Gate-Last?** - HKMG problem: High-k dielectrics (HfO2) degrade in quality at high temperatures (> 900°C). - S/D activation anneal: 1000–1100°C — would damage HfO2 if present. - Solution: Process transistor with dummy poly gate through high-T steps, then replace with final gate. **Gate-Last Process Flow** 1. **Gate First (Poly Dummy Gate)**: - Grow thin SiO2 interface layer. - Deposit polysilicon gate. - Pattern and etch gate stack. - Form spacers, S/D implant, activation anneal (poly survives high T). - PMD deposit and CMP to expose poly top. 2. **Gate Removal**: - Selectively wet-etch polysilicon (APM — NH4OH:H2O2:H2O). - Selective to SiO2 ESL, spacers: Poly:SiN selectivity > 100:1. - Reveals gate cavity — trench between spacers. 3. **Gate Replacement**: - ALD HfO2 (high-k dielectric, ~2nm). - ALD TiN (work function metal). - CVD W or CVD TiN fill (gate fill metal). - CMP to define gate height. **Advantages** - HKMG deposited at low T (200–300°C) → excellent interface quality, low Dit. - Multi-Vt metals can be patterned inside gate cavity without thermal degradation. - Silicide and S/D engineering done before gate replacement → no compromise. **Challenges** - Gate cavity fill: High AR (> 8:1) narrow gates → ALD step coverage critical. - Poly removal uniformity: Must be complete without damaging adjacent dielectrics. - Thermal budget management: All steps after gate removal must be low-T. The gate-last RMG process is **the standard integration scheme for all high-k/metal gate transistors from 32nm onward** — enabling the precise work function and interface quality that makes sub-32nm CMOS performance possible.