replacement metal gate rmg

**Replacement Metal Gate (RMG) Process** is the **gate-last integration scheme used in all advanced CMOS nodes from 45/32 nm onward — where a sacrificial polysilicon "dummy" gate is fabricated first, all high-temperature source/drain processing is completed, then the dummy gate is removed and replaced with the final high-k dielectric + metal gate stack at low temperature (<500°C), avoiding the thermal degradation of high-k/metal gate materials that made earlier gate-first approaches unsuitable for volume manufacturing**. **Why Gate-Last** The high-k metal gate (HKMG) stack is thermally sensitive: - HfO₂ crystallizes above ~500°C, creating grain boundaries that increase leakage. - Metal work function layers (TiN, TiAl) react with HfO₂ at high temperatures, shifting the effective work function by 100+ mV — destroying Vth control. - Source/drain activation anneal (>1000°C) would devastate the HKMG stack. The gate-last approach solves this by completing all high-temperature processing before depositing the HKMG stack. **Process Flow** 1. **Dummy Gate Formation**: Deposit SiO₂ (interfacial layer) + polysilicon + hardmask. Pattern and etch dummy gate with tight CD control. 2. **Spacer Formation**: Deposit and etch SiN spacers on dummy gate sidewalls. 3. **S/D Epitaxy**: Grow raised source/drain with in-situ doping. Full anneal at 900-1050°C to activate dopants. 4. **ILD0 Deposition**: Deposit interlayer dielectric (SiO₂ by PECVD or flowable CVD) to fill around the dummy gate. 5. **CMP Planarization**: Polish ILD0 flat, exposing the top of the dummy polysilicon gate. 6. **Dummy Gate Removal**: Selective etch removes polysilicon (NH₄OH or TMAH wet etch) and underlying SiO₂, leaving an empty gate trench defined by the SiN spacers. This is the critical "gate trench" that will receive the real gate. 7. **Interface Oxide Regrowth**: Grow ~0.5-1 nm SiO₂ on the exposed Si channel surface (chemical oxide or rapid thermal oxidation). This interfacial layer is essential for good mobility and reliability. 8. **High-k Deposition**: ALD HfO₂ (~1.5-2 nm, k~25) on the trench surfaces. Equivalent oxide thickness (EOT) target: 0.7-0.9 nm. 9. **Work Function Metal (WFM) Deposition**: ALD TiN, TiAl, TiAlC, TaN in precise sequences to set Vth for NMOS and PMOS separately. Different WFM stacks for different Vth flavors (SVT, LVT, uLVT). 10. **Gate Fill**: Tungsten (W) or cobalt (Co) fills the remaining trench volume. CMP removes overburden. **Multi-Vth Tuning** Modern SoCs require 3-5 threshold voltage (Vth) options for power-performance optimization: - **uLVT**: Fastest transistor, highest leakage. Thinnest TiN barrier. - **LVT**: Low Vth. Moderate TiN. - **SVT**: Standard Vth. - **HVT**: High Vth, lowest leakage. Thickest WFM stack. Each Vth requires a different WFM stack thickness, achieved through selective deposition/etch of TiN/TiAl layers using multiple patterning steps. **Challenges at Advanced Nodes** - **Gate Trench Scaling**: At 3 nm GAA, the gate length is 12-16 nm. The trench must accommodate: SiO₂ IL (~0.5 nm) + HfO₂ (~1.5 nm) + WFM (~2-4 nm) + fill metal — total: ~5-8 nm consumed by gate stack, leaving very little room for fill metal. - **Multi-Vth Complexity**: 4-5 Vth options × NMOS/PMOS = 8-10 different gate stack combinations, each requiring separate patterning and deposition steps. This adds 30+ process steps for WFM differentiation alone. The RMG Process is **the integration breakthrough that made high-k metal gates practical for high-volume manufacturing** — the gate-last strategy that elegantly decouples thermal processing from gate stack formation, enabling the precise threshold voltage control and gate dielectric quality that every advanced logic transistor depends on.