replacement metal gate

**Replacement Metal Gate (RMG)** is the **"gate-last" CMOS integration scheme where a sacrificial polysilicon dummy gate is used during front-end processing, then removed and replaced with the final high-k dielectric and metal gate stack after source/drain formation and high-temperature annealing are complete**. RMG enables the use of thermally sensitive metal gate materials that would degrade if exposed to the 1000°C+ activation anneals required for source/drain dopant activation. The RMG process flow proceeds as follows: a **dummy gate** of polysilicon (with a thin SiO2 interfacial layer beneath) is patterned and used to self-align the source/drain implants, spacer formation, epitaxial S/D growth, and silicidation — all standard CMOS front-end steps. After these high-temperature processes, an **interlayer dielectric (ILD0)** is deposited and planarized by CMP to expose the top of the dummy poly gate. The dummy poly is then selectively removed by wet etch (using TMAH or NH4OH), leaving a gate trench defined by the spacers. If the underlying SiO2 is also removed, the bare silicon channel surface is exposed for fresh interfacial oxide regrowth. Into this gate trench, the actual gate stack is deposited: an **interfacial layer (IL)** of ~0.5-1nm chemical SiO2, a **high-k dielectric** (HfO2 ~1.5-2nm by ALD), **work function metal (WFM)** layers — TiN, TaN, TiAl, or TiAlC in precise thickness combinations to set NMOS and PMOS threshold voltages — and finally a **fill metal** (typically tungsten or aluminum) to complete the gate electrode. CMP planarizes the metal to the ILD surface. The critical challenge in RMG is **dual work function engineering** — NMOS and PMOS transistors require different work functions (~4.1eV for NMOS, ~4.9eV for PMOS in silicon). This is achieved through selective deposition and removal of WFM layers using lithography and wet etch. For multi-threshold voltage (multi-Vt) products, additional WFM variations create 3-5 different Vt flavors, requiring complex patterning sequences within the gate trench. At GAA/nanosheet nodes, RMG becomes even more challenging: the gate metal must fill the ~8-12nm gaps between vertically stacked nanosheet channels while maintaining precise work function control. This requires **ALD-deposited WFM** with atomic-level thickness control and excellent conformality in extreme aspect ratio spaces. The gate fill in inter-sheet regions transitions from tungsten to materials like cobalt or ruthenium for better gap-fill capability. **Replacement Metal Gate is the foundational integration strategy that enabled the high-k/metal gate revolution starting at the 45nm node, and its complexity continues to escalate with each new transistor architecture from FinFET through nanosheet to CFET.**