k last process

**High-k Last** is an **HKMG integration variant where the high-k dielectric is deposited after the dummy gate is removed** — both the high-k and metal gate are formed in the replacement gate trench, ensuring neither is exposed to the high-temperature S/D anneal. **High-k Last Process** - **Dummy Gate**: Pattern dummy poly gate on a thin sacrificial oxide. - **S/D Processing**: Standard S/D formation and anneal (no high-k present yet). - **RMG**: Remove dummy poly AND sacrificial oxide → clean trench exposes the channel surface. - **Deposit Stack**: Deposit interfacial oxide + high-k + metal gate into the trench. **Why It Matters** - **Pristine High-k**: High-k is never exposed to high temperatures — maximum control over composition and thickness. - **Flexibility**: Can use high-k materials and compositions that are not thermally stable. - **Challenge**: The gate trench must be perfectly clean before high-k deposition — interface preparation is critical. **High-k Last** is **keeping the dielectric pristine** — depositing the high-k after all high-temperature processing for maximum material control.