gate-last (replacement gate)

**Gate-Last** (Replacement Metal Gate, RMG) is a **HKMG integration scheme where a sacrificial (dummy) gate is used during FEOL processing** — and then replaced with the actual high-k/metal gate stack after all high-temperature steps are complete, avoiding thermal degradation. **How Does Gate-Last Work?** - **Flow**: 1. Form dummy gate (SiO₂ + poly-Si). 2. Complete all FEOL (spacers, S/D implant, activation anneal, silicide). 3. Deposit ILD (interlayer dielectric), CMP to expose dummy gate top. 4. Remove dummy gate (wet/dry etch). 5. Deposit real high-k + metal gate into the trench. 6. CMP to planarize. **Why It Matters** - **Thermal Freedom**: The real gate stack never sees temperatures above ~400°C -> better control of work function and EOT. - **More $V_t$ Options**: More metal stack choices (materials that can't survive 1000°C are now available). - **Industry Standard**: Most foundries (TSMC, Samsung, GF) adopted gate-last from 28nm onward. **Gate-Last** is **the bait-and-switch of transistor fabrication** — using a placeholder gate during the hot steps and swapping in the real one at the end for maximum quality.