metal gate ald fill
**Metal Gate ALD Fill** is the **Atomic Layer Deposition process that deposits ultra-thin, conformal work-function and fill metals (TiN, TaN, TiAl, W, Co) inside the narrow gate trench of a high-k/metal gate transistor — replacing the sacrificial polysilicon gate with a precisely-engineered metal stack that sets the threshold voltage to within millivolts of the target value**.
**Why Metal Gates Replaced Polysilicon**
At the 45nm node, two problems forced the poly-to-metal transition: (1) Poly depletion — the polysilicon gate develops a thin depletion layer at the oxide interface, effectively adding ~0.4 nm to the gate oxide thickness and limiting capacitance scaling. (2) Fermi-level pinning — the poly work function cannot be independently tuned for NMOS and PMOS with high-k dielectrics, making Vth control impossible.
**The Replacement Metal Gate (RMG) Flow**
1. **Dummy Gate Removal**: The sacrificial polysilicon gate is selectively etched out, leaving an empty trench lined by the high-k dielectric (HfO2) and the spacer sidewalls.
2. **Interface Layer Re-Oxidation**: A thin (~0.3-0.5 nm) SiO2 chemical oxide is regrown at the Si/HfO2 interface to repair etch damage and improve carrier mobility.
3. **Work-Function Metal Deposition**: For NMOS: TiAl or TiAlC (work function ~4.1 eV) is deposited by ALD to pull the Fermi level toward the conduction band. For PMOS: TiN (work function ~4.7 eV) pulls toward the valence band. Multiple metal layers of precisely controlled thickness (0.5-2 nm each) set the exact Vth.
4. **Gate Fill**: The remaining trench volume is filled with a low-resistance metal (tungsten via CVD, or cobalt via ALD/CVD) to provide the gate electrode's electrical conductance.
5. **CMP Planarization**: Excess metal above the trench is removed by chemical-mechanical polish, leaving metal only inside the gate trench.
**ALD Requirements**
- **Conformality**: The gate trench in a nanosheet device has extreme geometry — metal must uniformly coat the top, bottom, and inner surfaces of 3-4 stacked nanosheets separated by 8-12 nm gaps. Only ALD achieves the required >95% step coverage.
- **Thickness Control**: A single ALD cycle deposits ~0.5 Angstroms. The difference between an NMOS Vth of 250 mV and 300 mV may be a single TiAl cycle — absolute thickness control at the monolayer level.
- **Nucleation Uniformity**: ALD precursors must nucleate uniformly on high-k, on nitride spacers, and on previously-deposited metal layers. Non-uniform nucleation creates Vth scatter across the die.
Metal Gate ALD Fill is **the atomic-precision metallurgy that defines the electrical personality of every transistor** — setting the threshold voltage that determines whether the device switches fast or slow, leaks little or much, at the scale of individual atomic layers.