hkmg gate

**High-k Metal Gate (HKMG) Technology** is the **gate stack engineering breakthrough that replaced silicon oxynitride (SiON, k~4-7) gate dielectric with hafnium-based high-k dielectric (HfO₂, k~22) and polysilicon gate electrode with metal gates (TiN, TiAl) — enabling aggressive equivalent oxide thickness (EOT) scaling below 1 nm while controlling gate leakage current, a transition that was mandatory at the 45 nm node and remains the foundation of all subsequent transistor technologies including FinFET and GAA**. **The SiO₂ Scaling Crisis** Gate capacitance = ε₀ × k × A / t_physical. Scaling transistors requires increasing gate capacitance (better channel control). With SiO₂ (k=3.9), this meant thinning the oxide. At 1.2 nm thickness (~5 atomic layers of SiO₂), quantum mechanical tunneling caused gate leakage currents exceeding 100 A/cm² — unacceptable for mobile devices and contributing significantly to total chip power. **High-k Solution** Using a material with higher dielectric constant (k) achieves the same capacitance with a physically thicker film: - EOT = t_high-k × (k_SiO₂ / k_high-k) = t_high-k × (3.9 / 22) for HfO₂ - A 1.5 nm HfO₂ film provides EOT ≈ 0.27 nm — physically thick enough to block tunneling while electrically behaving like a sub-1 nm SiO₂ film. **The Interfacial Layer Challenge** HfO₂ deposited directly on silicon creates a poor interface (high trap density, mobility degradation). A thin SiO₂ interfacial layer (IL, 0.3-0.8 nm) is retained between silicon and HfO₂. This IL is chemically grown or formed by scavenging — total EOT = EOT_IL + EOT_HfO₂. Reducing IL thickness below 0.5 nm (IL scavenging using TiN/TiAl gate electrodes that draw oxygen from the IL) is a key technique for scaling EOT below 0.7 nm. **Metal Gate Engineering** Polysilicon gates suffer from poly depletion (charge depletion layer near the gate-dielectric interface adds ~0.3-0.4 nm to EOT) and Fermi-level pinning with high-k dielectrics. Metal gates eliminate both issues: - **NMOS Work Function**: TiAl or TiAlC — work function near silicon conduction band edge (~4.1-4.3 eV) for low NMOS threshold voltage. - **PMOS Work Function**: TiN — work function near silicon valence band edge (~4.8-5.0 eV) for low PMOS threshold voltage. - **Multi-VT (Multi-Threshold Voltage)**: Modern processes offer 3-5 threshold voltage options (uLVT, LVT, SVT, HVT) by varying the metal gate stack composition and thickness. Each additional VT option requires extra dipole or work function metal layers and selective etch/deposition steps. **Replacement Metal Gate (RMG)** The gate-last (RMG) process dominates at FinFET and GAA nodes: 1. Form dummy polysilicon gate early in the process. 2. Complete S/D formation, contact etch stop layer, and ILD deposition. 3. Remove dummy poly gate (CMP + selective etch). 4. Deposit high-k + work function metals + gate fill metal in the resulting cavity. RMG avoids exposing the high-k dielectric to high-temperature S/D processing (>600°C) that would degrade its quality. HKMG is **the materials science revolution that saved transistor scaling** — the replacement of silicon's native oxide with engineered atomic-layer films that provide equivalent capacitance at physically viable thicknesses, enabling ten generations of technology scaling from 45 nm through the current 3 nm node and beyond.