halo implant

**Halo/Pocket Implant for Short Channel Effect Control** is the **angled ion implantation technique that locally increases doping concentration beneath the gate oxide near the source and drain edges of a MOSFET** — opposing the natural spreading of depletion regions from source and drain toward each other in short-channel devices, preventing drain-induced barrier lowering (DIBL) and threshold voltage rolloff that would make short-channel transistors leak excessively and exhibit poor off-state control. **Short Channel Effect (SCE) Problem** - Long-channel MOSFET: Gate controls entire channel potential → Vth independent of Lg. - Short-channel MOSFET (Lg < ~10× depletion depth): Source and drain depletion regions penetrate laterally → share charge with gate → gate loses control. - DIBL: High VDS pulls drain depletion deeper → lowers source-channel barrier → increases IOFF → Vth decreases with VDS. - Vth rolloff: Vth decreases as Lg decreases → hard to control IOFF at minimum Lg. **Halo Implant Solution** - Angled implant (7–30° tilt) of same-type dopant as well (p+ halo in nMOS, n+ halo in pMOS) near S/D edges. - Higher doping near S/D edges → raises electrostatic barrier → gate retains control of channel. - Counter-dopes local channel near junctions → raises Vth locally → reduces DIBL and Vth rolloff. - Pocket shape: Dopant concentrated near junction edge; decreases toward channel center. **Implant Parameters** - Species: B or BF₂ for n-type well halo; As or P for p-type well halo. - Energy: 20–80 keV → range 20–50 nm in Si (near junction). - Dose: 10¹² – 5×10¹³ ions/cm² → peak concentration 10¹⁷ – 10¹⁸ atoms/cm³. - Tilt angle: 7–30° → multiple rotations (0°, 90°, 180°, 270°) to cover both S and D sides. - Screen oxide: 2–5 nm oxide on surface → prevent surface damage, control implant depth. **Halo vs Anti-Punchthrough (APT) Implant** - APT: Deeper, vertical implant below the channel → stops depletion from reaching between S and D (punchthrough). - Halo: Shallower, angled → specifically targets lateral depletion near S/D edges. - Modern processes use both: APT for bulk channel doping + halo for lateral SCE control. **Trade-offs of Halo Implant** - Increases body effect (higher body doping near S/D) → VSB sensitivity increases. - Increases junction capacitance (higher n+ or p+ at junction) → speed penalty. - Well proximity effect (WPE): Halo dopants from adjacent wells can scatter → Vth variation near well edge. - Halo asymmetry: If S and D halos are not symmetric (one-sided implant, layout asymmetry) → directional Id-Vd asymmetry. **Halo in FinFETs** - FinFET: Narrow fin → high aspect ratio → angled implant shadow from fin. - Halo implant in FinFET: Very limited penetration under gate due to fin height → much less effective. - FinFET relies more on: Thin fin body (< 7 nm) for natural electrostatic control → less dependent on halo. - Nanosheet (GAA): No halo needed → gate-all-around provides intrinsic short channel control. **Process Integration** - Halo implant sequence: Gate patterning → gate spacer (thin) → angled halo implant → S/D extension implant → thick spacer → S/D implant → activation anneal. - Anneal trade-off: High temperature activates dopants but diffuses halo → abruptness lost → laser anneal or spike anneal at > 1000°C minimizes diffusion. Halo/pocket implants are **the electrostatic engineering technique that extended planar MOSFET scaling into the sub-100nm regime** — by locally boosting doping exactly where the gate is losing control to source and drain fringe fields, halo implants have enabled planar transistor operation at gate lengths that would otherwise be plagued by uncontrollable off-state leakage and Vth unpredictability, representing one of the most elegant examples of using implant engineering to compensate for fundamental geometric limitations in transistor operation, a technique that shaped the CMOS roadmap from the 130nm through 28nm nodes.