hard ip

Hard IP is a **pre-designed, pre-laid-out block** delivered as a fixed physical layout (GDS/OASIS) for a specific process technology. The customer places it in their chip design as-is—no modification allowed. **Hard IP vs. Soft IP** • **Hard IP**: Physical layout. Fixed for one process node. Optimized for best performance/area/power. Cannot be modified by the customer • **Soft IP**: RTL (Verilog/VHDL) source code. Portable across process nodes. Customer synthesizes and places it. Flexible but not optimized for a specific process **Common Hard IP Blocks** • **Memory compilers**: SRAM, ROM, register files. Tightly optimized for density and speed at each node • **I/O libraries**: Pad cells for chip-to-package connections (GPIO, power pads, ESD protection) • **SerDes**: High-speed serial transceivers (PCIe, USB, Ethernet). Analog-intensive, must be custom-designed per node • **PLLs**: Phase-locked loops for clock generation. Analog circuitry requiring per-node optimization • **ADC/DAC**: Analog-to-digital and digital-to-analog converters • **Standard cell libraries**: The basic gates used for digital design (also a form of hard IP) **Why Hard IP?** Analog and mixed-signal circuits **cannot be synthesized** from RTL—they must be custom-designed at the transistor level for each process node. A SerDes PHY operating at 112 Gbps requires precise transistor sizing, layout parasitic control, and careful shielding that can only be achieved through custom physical design. **Hard IP Business** Hard IP providers (Synopsys, Cadence, ARM, Alphawave) invest heavily to develop blocks for each foundry node. Customers pay **licensing fees** (upfront) and **royalties** (per chip shipped). The IP market exceeds **$7 billion** annually.