hardware emulation prototyping

**Hardware Emulation and FPGA Prototyping** are the **pre-silicon verification platforms that map an SoC design onto reconfigurable hardware (emulators or FPGA boards) to achieve execution speeds 100-10,000x faster than RTL simulation — enabling software development, system validation, and full-chip verification months before silicon arrives, where the ability to boot an operating system or run real application workloads on the design is impossible at simulation speeds of 1-100 Hz but feasible at emulation speeds of 100 KHz - 10 MHz**. **The Simulation Speed Wall** A modern SoC running at simulation speed (~10 Hz for a full-chip gate-level model) takes hours to execute a single millisecond of real time. Booting Linux requires billions of clock cycles — roughly 10 years at simulation speed. Emulation and FPGA prototyping overcome this by executing the design in actual hardware. **Hardware Emulation** - **Platforms**: Cadence Palladium Z2/Z3, Synopsys ZeBu EP1, Siemens Veloce Strato. Custom hardware containing arrays of programmable processors or FPGAs with optimized interconnect. - **Speed**: 100 KHz - 5 MHz (design clock equivalent). ~1000x faster than simulation. - **Capacity**: Up to 15-20 billion gates. Can model a complete SoC including CPU, GPU, memory controllers, and peripherals. - **Debug**: Full visibility into all signals at any point in time. Transaction-based recording, waveform dump on demand, and assertion monitoring. The primary advantage over FPGA prototyping. - **Use Cases**: Full-chip regression, firmware bring-up, hardware/software co-verification, performance validation, power estimation via activity capture. **FPGA Prototyping** - **Platforms**: Synopsys HAPS, Cadence Protium, or custom boards with AMD/Xilinx VU19P or Intel Stratix 10 FPGAs. - **Speed**: 10-100 MHz (near real-time for many designs). ~100,000x faster than simulation. - **Capacity**: Limited by FPGA capacity (~10M ASIC gates per FPGA). Multi-FPGA boards connect 4-8+ FPGAs for larger designs. - **Debug**: Limited visibility — internal signals require pre-configured probes (ChipScope/SignalTap). Iterating on debug probes requires hours of FPGA recompilation. - **Use Cases**: OS boot, driver development, real-world I/O connectivity (USB, Ethernet, PCIe), system-level performance benchmarking, demo to customers. **Compile Flow** 1. RTL is synthesized for the target platform (emulator processors or FPGA fabric). 2. Multi-FPGA partitioning splits the design across available devices, inserting time-domain multiplexing (TDM) on inter-FPGA links. 3. Constraints map I/O interfaces to physical connectors for real-world connectivity. 4. Compile times: 4-24 hours for large designs (FPGA P&R is the bottleneck). **Hardware Emulation and FPGA Prototyping are the time machines of chip development** — allowing design teams to validate hardware-software interaction and discover system-level bugs months before first silicon, compressing the critical path from tapeout to product launch.