hardware-software co-design

**Hardware-Software Co-Design** for edge AI is the **joint optimization of model architecture and hardware accelerator design** — designing the model to exploit hardware capabilities (parallelism, memory hierarchy) and the hardware to efficiently execute the target model workload. **Co-Design Dimensions** - **Model → Hardware**: Design custom hardware (NPU, ASIC) optimized for a specific model architecture. - **Hardware → Model**: Design model architectures that map efficiently to existing hardware (GPU, MCU, FPGA). - **Joint**: Simultaneously search the model architecture and hardware configuration space. - **Compiler**: Hardware-aware compilers (TVM, MLIR) bridge the gap between model and hardware. **Why It Matters** - **Efficiency**: Co-designed systems achieve 10-100× better energy efficiency than generic hardware running generic models. - **Edge Constraints**: Edge devices have strict power, area, and cost budgets — co-design is essential. - **Semiconductor**: Chip companies can co-design AI accelerators with target AI models for maximum performance per watt. **Co-Design** is **optimizing both sides together** — jointly designing the model and hardware for maximum edge AI performance and efficiency.