Base Logic Die

The base logic die is the bottom die of an HBM stack: the layer that aggregates every TSV column from the DRAM dies above it, runs the physical interface to the host, and handles test, repair and power management for the whole stack. With HBM4 it stops being a DRAM-process part and becomes a logic-process part, and that change reshapes both the architecture and the supply chain.

What it does

The DRAM core dies above it are optimised for bit density and nothing else. Everything that is not storing a bit lives on the base die:

  • the PHY driving 1024 or 2048 bits to the host across the interposer
  • TSV aggregation and per-channel routing from sixteen or more independent channels
  • built-in self-test, redundancy mapping and post-package repair
  • power management, on-die regulation, and thermal sensing
  • the direct-access test path that lets a stack be characterised before assembly

Why HBM4 moved it to a logic node

Through HBM3E the base die was fabricated on a DRAM-like process. DRAM processes are built around the capacitor and the retention budget; their transistors are comparatively slow and their metal stacks are thin. A 2048-bit PHY running at multi-gigabit rates is a large, fast, dense logic block, and building it on a DRAM process costs area and power that a logic process does not.

The energy argument is the decisive one. Interface energy is dominated by charging the channel capacitance each transition:

$$ E_{\text{bit}} = \alpha\, C_{\text{eff}} V_{DD}^{2} $$

A logic process offers both a lower $V_{DD}$ and denser, lower-capacitance wiring, and the quadratic in supply voltage means a modest voltage reduction is a large energy saving. Total interface power then scales as

$$ P_{\text{PHY}} = E_{\text{bit}} \times BW \times 8 $$

and at 2 TB/s that product is large enough that a fraction of a picojoule per bit decides whether the stack fits its thermal envelope. Thermal headroom is not abstract here: DRAM retention is exponential in temperature, so every watt dissipated in the base die shortens the refresh interval of the dies stacked directly above it.

HBM4 Base Logic Die: A Logic Part Under a Memory Stack two foundries, two process families, one stack DRAM core dies — memory foundry BASE LOGIC DIE PHY · TSV aggregation · BIST/repair · PMIC logic foundry — FinFET / nanosheet interposer — 2048-bit bus to host Energy per bit E_bit = α·C_eff·V²DD logic node → lower V, lower C quadratic in supply voltage Thermal coupling base die heat rises into DRAM retention is exponential in T refresh interval shortens → bandwidth lost

Custom base dies

Once the base die is a logic die, it can be customised per customer, and HBM4 is the generation where that becomes commercial practice. A buyer specifying their own base die can move function into the memory stack: scheduling and prefetch tuned to their access pattern, ECC schemes matched to their reliability target, compression and decompression at the memory boundary, and eventually arithmetic performed where the data already sits rather than after a round trip to the accelerator.

That last possibility is the interesting one. The bandwidth wall in transformer inference exists because weights must be streamed to the compute units and used once. Any operation that can be performed inside the stack removes traffic from the interface entirely, and the base die is the only place in an HBM stack with enough logic performance to host it.

What it costs

The stack is now a heterogeneous assembly spanning two foundries and two process families, bonded together, with yield and schedule coupled across companies that previously interacted only through a specification. A logic-node base die is also expensive relative to the DRAM above it, and it must be known-good before stacking, which raises the value of pre-bond test and post-package repair. Combined with the move from micro-bump to direct bond interconnect, HBM4 turns memory procurement into a co-design problem rather than a catalogue purchase — which is much of why HBM supply, not wafer capacity, has been the binding constraint on accelerator deployment.

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