HBM

# HBM Stack Vertical Thermal Gradient

An HBM stack packs eight or more DRAM dies directly on top of each other connected by through-silicon vias, and every die's heat has to pass through all the dies stacked above it before reaching a heat sink — which means the dies in the middle and bottom of the stack run measurably hotter than the dies at the top, purely as a consequence of stacking geometry, not because they're doing anything different. A planar DRAM chip dissipates heat straight down into the package and the board beneath it, with a short, direct thermal path. An HBM stack instead places multiple DRAM dies directly atop one another, and the dies lower in the stack have to conduct their heat upward through every die sitting above them before that heat finally reaches the heat sink attached to the top of the stack. Each additional die layer the heat has to pass through adds thermal resistance, so die temperature within a single HBM stack isn't uniform — it varies by vertical position, with the bottom logic die and lower DRAM dies running hottest.

This vertical thermal gradient matters because DRAM retention time — how long a cell can hold its charge before needing a refresh — gets worse at higher temperature, so the hottest dies in an HBM stack need more frequent refresh than the coolest ones, even though every die in the stack is otherwise identical silicon. A DRAM cell's leakage current increases with temperature, which directly shortens how long a cell retains valid charge before it needs to be refreshed. Because an HBM stack's bottom dies run hotter than its top dies purely from thermal-path geometry, those bottom dies experience faster charge leakage and need tighter refresh scheduling than the top dies do — identical hardware experiencing genuinely different reliability requirements purely because of where it physically sits in the stack.

Memory controllers managing HBM increasingly implement per-die or per-partition refresh rates rather than a single uniform refresh rate for the entire stack, specifically to avoid refreshing every die as often as the hottest die requires — a uniform worst-case refresh schedule would waste bandwidth and power refreshing the coolest dies far more often than their actual retention characteristics demand. Tuning refresh rate to each die's actual thermal position within the stack, rather than applying one conservative rate everywhere, recovers bandwidth and power that a blanket worst-case policy would otherwise sacrifice — directly turning knowledge of the stack's thermal gradient into usable system performance rather than treating it as a problem to be over-engineered around uniformly.

NAND flash's program disturb and erase disturb mechanisms described how electrical operations on neighboring cells degrade stored charge; HBM's vertical thermal gradient is DRAM's parallel problem, where a cell's physical position in a 3D stack — not any operation performed on it or its neighbors — determines how aggressively it needs to be refreshed, showing that 3D memory integration introduces position-dependent reliability variation regardless of whether the underlying storage technology is flash or DRAM.