Hmos 1978 Step 15 Die Cost Yield Economics Second Poly Layer

# Step 15 — Price the Yield and Die-Cost Consequence of Step 6's Second Polysilicon Layer

## 1. State the Cost Step 6 Named but Did Not Quantify

Step 6 of the base series redesigned HMOS's process flow around a second polysilicon layer, trading three additional mask levels for a substantial reduction in layout congestion and a corresponding density gain. That step argued the trade in layout terms — area saved versus masks added — and left the economic consequence of "masks added" implicit. Every additional mask level is an additional opportunity for a yield-limiting defect: particulate contamination, pattern distortion from the alignment error quantified in Step 12, or an incomplete etch, each of which can kill a die that would otherwise have passed. A simple, standard model treats each mask level as contributing an independent probability of a yield-limiting defect, so that overall die yield falls roughly geometrically with mask count, holding defect density per layer fixed:

$$Y\approx(1-d)^{N}$$

where $d$ is the per-layer defect probability for a die of a given area and $N$ is the number of mask levels. Moving from a six-mask single-polysilicon flow to Step 6's nine-mask double-polysilicon flow increases $N$ by three, and at any nonzero $d$ that is a real, multiplicative yield penalty — not a rounding error, and not something Step 6's layout-area argument alone captures.

Three Extra Masks Are Three Extra Chances to Lose a Die Y ≈ (1 - d)^N, each additional mask level multiplies, not adds, to the yield loss SIX-MASK SINGLE-POLY FLOW N = 6 pre-HMOS single-poly baseline fewer defect opportunities higher raw yield at fixed d NINE-MASK DOUBLE-POLY FLOW N = 9 (Step 6) three added mask levels three added defect opportunities lower raw yield at the same d N = 6, higher Y N = 9, lower Y at same d WHAT STEP 6 ARGUED VS. WHAT THIS STEP ADDS Step 6: three extra masks buy a layout-area reduction worth having this step: those same three masks also multiply the yield penalty, a cost the layout argument omits the net decision requires both numbers, not the area number alone

## 2. Weigh the Yield Loss Against the Area Gain to Recover Step 6's Real Net Benefit

The decision Step 6 actually made is only sound if the die-area reduction it bought is worth more, in cost per good die, than the yield penalty quantified above costs. Cost per good die scales as the cost of processing one wafer through the full flow, divided by the number of good dies that wafer yields — and the number of good dies depends on both how many dies fit on the wafer (smaller die area, from Step 6's density gain, raises this) and what fraction of them pass (lower with three added masks, from this step's yield penalty, which lowers this). A smaller die that yields acceptably still wins on cost per good die as long as the area reduction's effect on die-per-wafer outweighs the yield reduction's effect on the passing fraction — which, at defect densities typical of a maturing but not yet fully optimized nine-mask flow in 1978, it generally did, which is exactly why Intel committed to the Step 6 flow for volume production rather than treating it as a research curiosity.

That outcome was not guaranteed in advance, and it is the reason yield ramp, not just design completion, was its own multi-month engineering effort after Step 6's process flow was finalized: every additional mask level's defect density had to be driven down through normal process learning before the area gain's cost advantage could actually be realized at the die-cost level rather than only on paper. The lesson this step adds to the extension is that a process redesign's layout-area argument and its manufacturing-cost argument are related but distinct, and HMOS's second-poly flow had to win on both, not just the first, before it could ship as the volume process behind the 8086.

Cost per Good Die: Two Effects Pulling in Opposite Directions DIE-PER-WAFER EFFECT Step 6's area reduction more dies fit per wafer pulls cost per good die down favors the nine-mask flow PASSING-FRACTION EFFECT three added mask levels lower fraction of dies pass pulls cost per good die up favors the six-mask flow WHICH EFFECT WON, AND WHY IT TOOK MONTHS TO CONFIRM at 1978's maturing nine-mask defect densities, the area effect outweighed the yield effect — but only after a normal process-learning ramp drove each new mask level's defect rate down Intel's commitment to Step 6's flow for the 8086 rested on this ramp completing on schedule

## 3. Place This Step in the Extension's Own Lineage

This step completes an economic accounting Step 6 of the base series opened but left half-finished: the layout-area benefit of the second-polysilicon flow is real, but it is only a net win once the yield penalty from three additional mask levels — compounded, as Step 12 already showed, by 1978's contact-aligner registration tolerance — is weighed against it. Both effects were real; the historical record is that the area effect won, but only after a process-learning ramp, not automatically on the first wafer lot. Step 16 turns from the microprocessor applications this extension has focused on so far to a different HMOS product line entirely: the SRAM and memory parts built in the same process, where the design priorities were never about ratioed-logic current matching at all.

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