Hmos 1978 Redesign Process Flow for Second Polysilicon Layer

# Step 6 — Redesign the Process Flow for a Second Polysilicon Layer

## 1. The Layout Congestion Crisis of Single-Poly NMOS

To compress microprocessor cell areas and eliminate parasitic routing underpasses, the HMOS process flow was redesigned to incorporate a second level of polysilicon (Poly 2), trading increased fabrication complexity for layout density. In Step 5, we saw how the interconnect resistance-capacitance (RC) delay collided with nanosecond transistor switching. But circuit designers faced an equally severe physical roadblock: topological routing congestion.

In standard mid-1970s NMOS processing, fabs provided only a single layer of doped polysilicon (Poly 1) and a single layer of aluminum metallization (Metal 1). This single-poly architecture imposed severe geometric penalties:
* The Wire-Crossing Penalty: Two Poly 1 signal traces could not cross without forming a short circuit. When signal paths intersected, one trace was forced to drop down into an $N^+$ diffused silicon tunnel in the substrate. These diffused underpasses introduced heavy junction capacitance ($C_j \approx 0.5\ \text{fF}/\mu\text{m}^2$) and high series resistance ($R_{\Box,\text{diff}} \approx 30\text{ to }50\ \Omega/\Box$), degrading signal edge rates.
* The Cumbersome Butting Contact: In a depletion-load inverter (Steps 2 and 3), the load transistor’s gate must connect directly to its own source ($V_{GS,L} = 0$). In single-poly NMOS, this connection required a "butting contact"—a giant, un-passivated contact cut where aluminum draped over the edge of the Poly 1 gate to touch the $N^+$ silicon diffusion. Because the metal had to overlap both the poly step edge and the active silicon without spiking through the junction, butting contacts demanded massive design-rule spacing margins, swelling inverter cell footprints.

By introducing a second polysilicon layer (Poly 2) separated from Poly 1 by an inter-poly dielectric (IPD), fabs unlocked true multi-layer silicon wiring: Poly 2 could route over Poly 1 gates freely, and direct buried contacts replaced bloated aluminum butting contacts.

Single-Poly vs. Double-Poly Architecture replacing bloated aluminum butting contacts with self-aligned Poly 1 / Poly 2 multi-layer routing 1974 SINGLE-POLY NMOS: BUTTING CONTACT P-Substrate N+ Diffusion Poly 1 Gate Aluminum Butting Contact Layout Span: > 16 µm (Bloated!) Single-Poly Penalties: • Massive contact clearance rules • Aluminum junction spiking risk 1978 DOUBLE-POLY HMOS: COMPACT STRAP P-Substrate N+ Diffusion Poly 1 Poly 2 Strap Layout Span: 8 µm (50% Area Savings!) Double-Poly Advantages: • Direct poly-to-poly contact • Free wire-crossing without substrate tunnels THE STRUCTURAL LEVER OF DOUBLE-POLYSILICON ✓ Topological Freedom: Poly 2 crosses Poly 1 without dropping into high-capacitance diffused substrate tunnels ✓ Density Transformation: Slashes load resistor and SRAM cell areas by 40% to 50% across the microprocessor Double-poly was the manufacturing price paid to fit 29,000 transistors onto the Intel 8086 die.

## 2. Mask-Count Cost Accounting and the Process Flow Ledger

Integrating a second polysilicon layer transformed the manufacturing ledger, paralleling the mask-count cost accounting of 3D memory scaling.

Process Flow Ledger: Single-Poly vs. Double-Poly HMOS accounting mask additions, thermal budgets, and inter-poly dielectric reliability 1974 SINGLE-POLY NMOS (6 MASKS) Mask 1: LOCOS Active Area Isolation Mask 2: Depletion Threshold Implant (VTD) Mask 3: Poly 1 Gate Definition Mask 4: Contact Cut (BPSG Dielectric) Mask 5: Aluminum Metal 1 Metallization Mask 6: Passivation / Pad Opening Total: 6 Photolithography Masks 1978 DOUBLE-POLY HMOS (9 MASKS) Mask 1: LOCOS Active Area Isolation Mask 2: Dual Threshold Ion Implant (B⁺ / As⁺) Mask 3: Poly 1 Gate & First Routing Layer ✚ Mask 4: Buried Contact Cut (Direct to Si/Poly 1) ✚ Mask 5: Poly 2 Definition & Interconnect Mask 6: Self-Aligned S/D Ion Implantation Mask 7: Contact Cut (BPSG Dielectric) Mask 8: Metal 1 Metallization Total: 9 Masks (+50% Lithography Cost) The Process Accounting Tradeoff: HMOS added 3 photolithography masks, inter-poly oxidation, and stringer etching, but bought back a 2× density improvement essential for 16-bit microprocessors.

## 3. Place This Step in the Project's Own Lineage

Step 6 bridges electrical optimization with physical manufacturing complexity:
1. The Cost of Density: Steps 1 through 4 optimized the transistor itself (electric fields, implant-tuned depletion loads, and 70 nm gate oxides). Step 5 confronted the interconnect wire. Step 6 tallies the exact process cost: single-poly NMOS required only 6 masks, while double-poly HMOS required 9 masks ($+50\%$ lithography overhead). Just as 1974 DRAM paid in deep trench etching and CMP passes, 1978 microprocessor NMOS paid in a second polysilicon layer.
2. Eliminating the Butting Contact Hazard: Replacing single-poly aluminum butting contacts with self-aligned Poly 2 direct straps eliminated one of the primary yield killers of early semiconductor manufacturing: aluminum junction spiking. This reliability enhancement enabled higher manufacturing yields for massive 16-bit microprocessor dice.
3. Leading to the Direct Comparison: With the complete device, oxide, silicide, and double-poly architecture in place, we can now evaluate the total system payoff. Step 7 performs the definitive benchmark: measuring clock-speed, power, and die area of HMOS directly against standard 1974 NMOS at the same lithography generation.

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