What Is an Etch Polysilicon Filmstack

An etch polysilicon filmstack (etch polysilicon etch filmstack) is an engineered multi-layer material stack designed for high-fidelity pattern transfer in replacement metal gate (RMG) dummy poly structures, 3D NAND floating gates and control gates, and planar CMOS transistor electrodes. In advanced semiconductor manufacturing, polycrystalline silicon (poly-Si) serves either as an active conductive gate conductor or as a sacrificial structural mandrel that defines the channel length ($L_g < 12\text{ nm}$) before being dissolved and replaced by work-function metals. The etching of a polysilicon filmstack represents one of the most critical anisotropic dry etch sequences in microelectronics: the plasma must transfer sub-nanometer critical dimension (CD) features from lithographic hardmasks through 40 nm to 100 nm of doped poly-Si, achieving vertical sidewall angles ($89.5^\circ\text{–}90.0^\circ$) while terminating on an ultra-thin ($<1.2\text{ nm}$) gate oxide or interfacial layer with near-infinite selectivity ($>150:1$). Managing this filmstack requires precise coordination between multi-layer hardmasks (photoresist, bottom anti-reflective coating, and silicon dioxide or silicon nitride caps), halogen etch chemistries ($HBr/Cl_2/O_2/CF_4$), and surface passivation kinetics ($SiO_xBr_y$) to prevent micro-trenching, footing, and gate-dielectric punch-through. At a high level, the architectural anatomy of a polysilicon gate filmstack and its selective dry etch sequence looks like this:

Substrate preparation
Pristine Si substrate with 1.0-1.5nm gate oxide (SiO2/SiON)
Poly-Si & hardmask deposition
60-100nm LPCVD Poly-Si + 20nm SiN / SiO2 hardmask
Polysilicon filmstack multi-step dry etchBreakthrough, bulk anisotropic clearing, and soft-landing selectivity
Hardmask open & breakthrough
CF4 / CH2F2 punch-through of native oxide & SiN cap
High-rate bulk main etch
Cl2 / HBr / O2 anisotropic etching (profile angle 89.8°)
Dynamic sidewall passivation
SiOxBry passivating film suppresses lateral undercut
High-selectivity soft landing
Pure HBr / O2 / He chemistry (>150:1 selectivity to SiO2)
↻ atomic layer endpoint handoff
Zero gate-oxide punch-through
Retains continuous 1.0nm gate dielectric with zero Si recess
Sub-12nm gate CD integrity
Enables uniform threshold voltage across logic and memory

A few principles are essential for understanding how polysilicon etch filmstacks are constructed, how their halogen plasma chemistry achieves vertical sidewalls, and why surface oxidation kinetics govern selectivity over ultra-thin gate oxides:

Filmstack structural hierarchy and layer functions. In advanced CMOS and memory fabrication, a polysilicon etch filmstack is arranged in five functional strata from top to bottom:
1. *Lithographic Patterning Cap:* Photoresist and silicon-containing bottom anti-reflective coating (Si-BARC) or spin-on carbon (SOC) defining the critical dimension.
2. *Dielectric Hardmask (DHM):* $15\text{ to }30\text{ nm}$ of low-stress silicon nitride ($Si_3N_4$) or silicon dioxide ($SiO_2$) deposited via PECVD. The hardmask resists halogen plasma erosion during the poly etch, preventing CD blooming and facet transfer.
3. *Polysilicon Core Layer:* $40\text{ to }100\text{ nm}$ of undoped or in-situ doped ($n^+$ phosphorus/arsenic or $p^+$ boron) polycrystalline silicon deposited via low-pressure chemical vapor deposition (LPCVD) at $620^\circ\text{C}$. Grain boundary morphology, grain size distribution ($10\text{–}30\text{ nm}$), and dopant concentration directly modulate the local chemical etch rate.
4. *Gate Dielectric / Interfacial Layer:* $1.0\text{ to }1.5\text{ nm}$ of thermally grown silicon dioxide ($SiO_2$), silicon oxynitride ($SiON$), or high-$k$ interfacial oxide ($SiO_x$). This fragile barrier must remain completely intact after poly removal.
5. *Single-Crystal Silicon Substrate:* Active transistor channel (bulk Si or silicon-on-insulator SOI) where zero recess (<0.2 nm) is permitted.

Polysilicon Gate Etch Filmstack Architecture Layer stack hierarchy, HBr/Cl2/O2 passivation kinetics, and gate oxide selectivity Gate Poly Filmstack Layers SiN / SiO2 Hardmask (25nm) Polysilicon Core (70nm) LPCVD Poly-Si (Doped n+/p+) SiOxBry Passivated Sidewalls Gate Oxide (SiO2 / SiON, 1.2nm) Silicon Channel (Substrate) Zero Recess Tolerance (<0.2nm) L_g CD Control < 0.5nm 3σ Multi-Step Plasma Reaction & Selectivity Dynamics 1. Breakthrough Step (CF4 / CH2F2 / Ar): Strips 1-2nm native oxide; fluorocarbon ions clear surface uniformly 2. Anisotropic Bulk Etch (Cl2 / HBr / O2): Si + 2Cl2 → SiCl4 ↑ | Si + 4HBr + O2 → SiBr4 ↑ + SiOxBry (passivation) High rate (~200 nm/min); creates 89.8° vertical profile without bowing 3. Soft Landing & Over-Etch (HBr / O2 / He): HBr does not spontaneously etch SiO2; O2 regenerates oxide surface Selectivity Poly:SiO2 > 150:1 | Eliminates footing and microtrenching CD Uniformity: < 0.6 nm 3σ | Sidewall Angle: 89.8° ± 0.3° HBr / Cl2 / O2 Synergy Balances etch rate & CD slope >150:1 Selectivity to SiO2 Protects 1.2nm gate dielectric SiOxBry Passivation Eliminates lateral undercut polysilicon etch filmstacks employ Cl2/HBr/O2 to build dynamic SiOxBry sidewall films that lock 90° gate profiles pure HBr/O2 soft landing provides >150:1 selectivity to preserve the ultra-thin 1.2nm gate dielectric without pitting

Etch mechanisms: chlorine, hydrogen bromide, and oxygen synergy. Etching a polysilicon gate requires three coordinated plasma regimes:
- *Breakthrough (BT):* Native silicon oxide ($1\text{ to }2\text{ nm}$ of $SiO_2$) inevitably grows atop polysilicon upon atmospheric exposure. A short ($2\text{–}4\text{ s}$) low-pressure $CF_4/CH_2F_2/Ar$ step rapidly punches through this native oxide with minimal hardmask loss.
- *Main Etch (ME):* Fast, directional etching is driven by a mixture of chlorine ($Cl_2$) and hydrogen bromide ($HBr$):

$$Si(s) + 2Cl_2(g) \rightarrow SiCl_4(g) \uparrow \quad ; \quad Si(s) + 4HBr(g) \rightarrow SiBr_4(g) \uparrow + 2H_2(g) \uparrow$$

Chlorine provides high chemical reactivity and fast vertical etch rates ($>200\text{ nm/min}$). However, chlorine radicals can etch silicon spontaneously without ion assistance, leading to lateral profile undercut. Adding $HBr$ and trace oxygen ($O_2$) causes volatile silicon bromides and oxygen radicals to react on feature sidewalls, forming a self-limiting silicon oxybromide passivation layer ($SiO_xBr_y$). Because energetic ions impinge only vertically, this protective film remains intact on sidewalls, locking vertical profile angles ($89.8^\circ \pm 0.3^\circ$).
- *Soft Landing (SL) & Over-Etch (OE):* When the poly clears to within 5 nm of the gate oxide, the chemistry shifts to chlorine-free $HBr/O_2/He$ with reduced RF bias power. Bromine radicals cannot chemically break strong silicon-oxygen bonds ($Si-O \approx 799\text{ kJ/mol}$), and the oxygen feed continuously oxidizes any exposed gate dielectric, driving etch selectivity of poly-Si over $SiO_2$ above $150:1$. This enables complete removal of residual poly footings without gouging the active silicon substrate.

Read an etch polysilicon filmstack through an *architectural-scaffolding* lens: a precisely balanced structural column where halogen gases cut vertical channels at nanoscale precision, protected by self-assembling oxybromide shields, and brought to a dead stop on an atomic monolayer of gate oxide.

Take what is an etch polysilicon filmstack further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app