poly-silicon deposition

Polysilicon deposition by CVD creates polycrystalline silicon films used for transistor gates, interconnects, and other structural elements. **Process**: Thermal decomposition of silane (SiH4) at 580-650 C in LPCVD furnace. SiH4 -> Si + 2H2. **Temperature dependence**: Below ~580 C: amorphous silicon. 580-650 C: polysilicon with small grains. Higher temperature: larger grains. **Grain structure**: As-deposited grain size typically 20-100nm. Grain size affects electrical and mechanical properties. **Doping**: In-situ doping with PH3 (n-type) or B2H6 (p-type) during deposition. Or post-deposition implant and anneal. **Gate application**: Polysilicon gate electrode was standard for decades. Now largely replaced by metal gate in advanced nodes (high-k/metal gate). **Resistor**: Doped polysilicon used for precision resistors. Sheet resistance tuned by doping level. **Thickness**: Gate poly typically 50-150nm. Thicker for other applications. **Batch processing**: LPCVD deposits on 100+ wafers simultaneously. High throughput. **Grain boundary effects**: Grain boundaries affect carrier mobility, diffusion, and roughness. **Surface roughness**: Poly surface roughness affects subsequent lithography and interface quality. **Alternatives**: Amorphous silicon deposited at lower temperature, then crystallized by anneal for controlled grain structure.