polysilicon gate deposition

**Polysilicon Gate Deposition and Patterning** is the **CMOS process module that deposits and patterns the doped polysilicon (poly) layer that serves as the gate electrode in traditional gate-first integration or as a sacrificial mandrel in replacement metal gate (RMG) processes** — with poly CD (critical dimension) directly setting the transistor gate length, making poly deposition uniformity, photoresist patterning, and etch profile control among the most critical process steps in CMOS manufacturing. **Polysilicon Deposition (LPCVD)** - Precursor: SiH₄ (silane) at 600–630°C, pressure 0.1–1 Torr → amorphous Si or poly-Si. - Below 580°C: Amorphous silicon → annealed above 900°C → recrystallizes to poly. - 580–630°C: Poly-Si directly → preferred for gate (established grain structure). - Thickness: 100–150 nm for gate poly (must survive etch and silicidation without full consumption). - Uniformity: ±1% thickness across 300mm wafer → critical for CD control via reflectometry endpoint. **In-Situ vs Ex-Situ Doping** - **In-situ doped**: PH₃ (n-type) or B₂H₆ (p-type) added during deposition → doped during growth. - Advantage: Uniform doping, no additional implant step. - Disadvantage: Changes deposition rate and grain structure; n/p poly cannot be different in same deposition run. - **Ex-situ (implant doped)**: Undoped poly → separate B or P implant → more control over doping level. - Common for gate poly: Separate doping steps for n-poly (NMOS gate) and p-poly (PMOS gate) in CMOS. - Doping level: 10²⁰ – 10²¹ atoms/cm³ → degenerate semiconductor → metal-like conductivity. **Hard Mask and ARC for Gate Patterning** - Gate patterning demands: Best CD control in entire process → dedicated hardmask + photoresist. - Stack: Poly / SiO₂ hard mask / SiON or BARC / photoresist. - Hard mask function: Etch resist during poly etch (photoresist can't survive long poly etch). - ARC (Anti-Reflective Coating): Reduce standing wave and CD variation from reflection at poly/oxide interface. **Gate Poly Etch** - Chemistry: HBr/Cl₂ main etch → profile control; Cl₂ for lateral etch rate control. - Selectivity requirements: - Poly over gate oxide (SiO₂): > 50:1 selectivity → stop etch without consuming thin gate oxide (< 3 nm). - Poly over STI (SiO₂): Same selectivity → avoid STI erosion. - Profile: Near-vertical sidewall (89–90°) → precise CD transfer from resist to poly. - Over-etch: 10–20% over-etch to clear residues → must not penetrate gate oxide. - CD bias: Poly CD = resist CD - CD bias (from etch loading, plasma, etch profile) → calibrate in OPC. **Poly CD Uniformity** - Gate length variation → Vth variation → circuit speed spread. - Within-wafer CDU (CD uniformity): Target < ±3% (3σ) at 45nm node → < ±1% at 7nm (EUV). - Loading effects: Dense poly array etches differently than isolated poly → OPC correction. - Poly line edge roughness (LER): Line edges not straight → LER → random Lg fluctuation → Vth variation. **Dummy Gates and Gate Density Rules** - Optical lithography: Best poly CD near target pitch → isolated poly prints at different CD than dense. - Dummy gate fill: Fill open areas with non-functional poly gates → improve optical proximity consistency → better CDU. - Design rules: Minimum gate density rule → ensures CDU within spec; maximum gate space rule → avoids OPC issues. **Poly in Replacement Metal Gate (RMG) Flow** - RMG: Poly gate is dummy → patterned and etched → source/drain epi and silicide formed → dielectric fill → CMP planarize → poly selectively removed → metal gate deposited in void. - Advantage: Metal gate deposited last → avoids high-temperature degradation of metal work function. - Poly removal: H₃PO₄ or TMAH (wet) or H₂/Cl₂ (dry) → high selectivity poly over SiO₂. Polysilicon gate deposition and patterning are **the pattern-definition steps that set the fundamental transistor gate length with sub-nanometer accuracy** — because every 1nm variation in gate poly CD translates to a measurable Vth shift and drive current change, achieving ±0.5nm CD uniformity across a 300mm wafer using optimized LPCVD deposition followed by hard-mask-protected plasma etching with carefully calibrated OPC corrections represents one of the most precise manufacturing achievements in high-volume fabrication, one that enabled CMOS scaling from the 1µm through the 28nm planar node before replacement metal gate and EUV took over at finer dimensions.