Hmos 1978 Confront Interconnect Faster Transistor Faster Wire

# Step 5 — Confront the Interconnect: Why a Faster Transistor Needs a Faster Wire

## 1. The Historical Crossover: When the Wire Overtook the Gate

As gate delay dropped into the single-nanosecond regime, on-chip interconnect resistance-capacitance (RC) delay became comparable to transistor switching speed for the first time. In Step 1 through Step 4, we tracked the aggressive device-level optimization of Intel HMOS: decoupling thresholds via ion implantation, sizing aspect ratios for ratioed logic, and thinning the gate dielectric to $70\ \text{nm}$. Together, these innovations slashed intrinsic gate delay from the $10\text{--}20\ \text{ns}$ typical of 1974 NMOS down to $1.0\ \text{ns}$ in 1978 (and $400\ \text{ps}$ in HMOS-II).

However, a digital processor is not an isolated cluster of transistors; it is an integrated network connected by miles of microscopic conductive tracks. In early microprocessors (such as the 1971 Intel 4004 or 1974 8080), transistors were so sluggish that wiring transit time was completely negligible:

$$t_{\text{wire}} \ll t_{\text{gate}} \quad (1974\text{ Regime})$$

In 1978, with the arrival of the 29,000-transistor Intel 8086 and complex 16-bit architectures, die size expanded while wires narrowed to $3.5\ \mu\text{m}$. Under classical geometric scaling by factor $\kappa$:
* Transistor Delay Scales Down: $\tau_{\text{gate}} \propto 1/\kappa$
* Interconnect Resistance Per Unit Length Soars: $R_{\text{wire}} = \rho L_w / (W_w H_w) \propto \kappa^2$
* Interconnect Capacitance Per Unit Length Stays Flat: $C_{\text{wire}} \approx \varepsilon_{\text{ox}} W_w / t_{\text{fox}} \propto 1$

For global lines whose physical span across the chip does not scale down ($L_w \approx \text{constant}$), distributed Elmore delay scales quadratically with length:

$$\tau_{\text{wire}} \approx \frac{1}{2} R_{\text{wire}} C_{\text{wire}} = \frac{1}{2} \left(\frac{\rho L_w}{W_w H_w}\right) \left(\varepsilon_{\text{ox}} \frac{W_w L_w}{t_{\text{fox}}}\right) = \frac{1}{2} \frac{\rho \varepsilon_{\text{ox}}}{H_w t_{\text{fox}}} L_w^2$$

As linewidths narrowed, the distributed RC delay of long global wires escalated precisely while transistors accelerated, causing a historic collision where the interconnect began to dominate the clock cycle.

The Historical Crossover: Gate Delay vs. Interconnect RC Delay how the 1978 HMOS revolution triggered the first wiring bottleneck in semiconductor history SCALING DELAY DIVERGENCE (1974 → 1980) Scaling Progress (Lithography) Delay (ns) 1974 (6 µm) 1978 (3.5 µm) 1980 (2.0 µm) τgate (Plunging: 15 ns → 1 ns) τwire (Rising RC) 1978 CROSSOVER τwire ≈ τgate The Turning Point in Chip Architecture: • Prior to 1978: designers spent 95% of timing effort on gate logic • After 1978: interconnect transit time dictated the system clock rate THE SCALING ASYMMETRY Transistor Delay: Wins Under Scaling • Channel shrinks: L → L / κ • Delay drops: τgate ∝ L2 / μ → τ / κ Wire RC Delay: Loses Under Scaling • Wire cross-section: Aw → Aw / κ2 • Resistance shoots up: R ∝ κ2 • Global RC delay: τwire ∝ R · C → κ2 ! The Microprocessor Reality: A 5 MHz 8086 processor clock period is 200 ns. A single unbuffered poly run burned 15 ns of that budget. THE FIRST INTERCONNECT WALL ✓ Speed Reversal: Device speed gained 10× while interconnect resistance worsened by 4× ✓ Architecture Mandate: Eliminating high-resistance polysilicon signal runs became an absolute necessity Step 5 marks the historical moment when chip architects had to start co-designing wires alongside transistors.

## 2. The Polysilicon Bottleneck and the Refractory Silicide (Polycide) Solution

In 1970s NMOS manufacturing, only one layer of aluminum metallization was available, which had to be reserved for primary $V_{dd}$, $\text{GND}$, and data bus distribution. Long secondary routing lines—especially memory word lines and random logic interconnects—were implemented in doped polysilicon.

Doped polysilicon has an extraordinarily high sheet resistance:

$$R_{\Box,\text{poly}} \approx 20\text{ to }40\ \Omega/\Box \quad \text{vs.} \quad R_{\Box,\text{Al}} \approx 0.03\ \Omega/\Box \quad (1,000\times\text{ disparity})$$

A $1\ \text{mm}$ polysilicon line with linewidth $W = 3.5\ \mu\text{m}$ contains $N_{\Box} = 1000 / 3.5 \approx 285\ \text{squares}$. At $30\ \Omega/\Box$, the line resistance alone reaches $8.5\ \text{k}\Omega$. Driving a typical distributed gate load of $1.5\ \text{pF}$ creates an RC delay of:

$$\tau_{\text{RC}} \approx 0.5 \times (8.5\ \text{k}\Omega) \times (1.5\ \text{pF}) \approx 6.4\ \text{ns}$$

While a local HMOS inverter switched in $1.0\ \text{ns}$, propagating that signal across a single millimeter of polysilicon added over $6\ \text{ns}$ of latency.

The Polysilicon Bottleneck and the Polycide Revolution replacing 30 Ω/sq doped poly with refractory metal silicide shunts and contact stitching STANDARD POLYSILICON LINE (30 Ω/□) Gate 1.0 ns 2.8 kΩ 2.8 kΩ 2.8 kΩ End Node +6.4 ns! 1 mm Poly Routing Performance: • Total Line Resistance: Rwire ≈ 8,500 Ω • Line Capacitance: Cwire ≈ 1.5 pF • Propagation Delay: τRC = 6.4 ns (6× slower than gate!) Severely distorts pulse edges and limits clock rate. THE POLYCIDE SHUNT SOLUTION (1.5 Ω/□) Doped Polysilicon Base (Preserves VT Work Function) Refractory Silicide Shunt (WSi₂ / TiSi₂): 1.5 Ω/□ Polycide Engineering Payoff: • Resistance slashed 20×: Rwire drops from 8,500 Ω to 425 Ω • RC propagation delay plunges: 6.4 ns → 0.32 ns ✓ Wire latency drops below intrinsic gate switching speed Preserved timing margins for Intel 8086 / 8088 8 MHz clocking. The Interconnect Resolution: By shunting polysilicon with refractory metal silicides (WSi₂), HMOS brought interconnect latency back under control, ensuring wire delays kept pace with nanosecond transistors.

## 3. Place This Step in the Project's Own Lineage

Step 5 documents the transition of scaling theory from a device discipline into a complete circuit system discipline:
1. The Interconnect Dimension Enters the Story: Step 1 established the field constraint ($E = V/L$), Step 2 and 3 solved ratioed logic current matching, and Step 4 accelerated transconductance via gate oxide thinning ($t_{\text{ox}} = 70\ \text{nm}$). Step 5 introduces the first systemic roadblock external to the transistor: the resistance of the interconnect wire ($R_{\Box,\text{poly}} \approx 30\ \Omega/\Box$), which exploded quadratically with scaling.
2. The Birth of Materials Engineering in Metallization: Up through 1974, silicon processing relied exclusively on single-crystal silicon, thermal oxide, and aluminum. Step 5 demonstrates the moment fabs were forced to adopt refractory metal silicides (such as tungsten silicide $\text{WSi}_2$ and titanium silicide $\text{TiSi}_2$) to construct composite "polycide" gate electrodes, cutting sheet resistance from $30\ \Omega/\Box$ down to $1.5\ \Omega/\Box$.
3. Leading to Multi-Layer Wiring Complexity: Even with silicide shunting, single-level aluminum wiring became physically congested. In Step 6, we examine the next major structural evolution of the HMOS process flow: introducing a second polysilicon layer (Poly 2) and contact architectures to route dense microprocessors.

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