Deep Submicron CMOS Scaling 1990s Reduce Sheet Resistance with Silicide

# Deep Submicron CMOS Scaling (1990s): Step 7 — Reduce Polysilicon and Diffusion Sheet Resistance With Silicide

## 1. A Resistance Problem That Scaling Makes Worse, Not Better

Polysilicon gate lines and diffused source/drain regions both carry current laterally over some distance before reaching a contact, and their sheet resistance (resistance per square of material) sets how much voltage drop and delay that lateral run adds. As deep submicron scaling shrank line widths, the cross-sectional area available for current to flow through shrank too, while the lengths of gate and diffusion runs needed to reach contacts did not shrink proportionally — so sheet resistance per unit length rose generation over generation even as the devices themselves got faster, risking a resistance bottleneck that could cancel out the switching-speed gains Steps 1 through 6 worked to preserve.

## 2. Why Doping Alone Cannot Fix It

Diffusion sheet resistance can be lowered somewhat by higher dopant concentration, but concentration is already constrained by the LDD grading from Steps 3 and 4 and by solid solubility limits in silicon — there is only so much dopant that can be driven into the diffusion before diminishing returns and crystal damage set in. Polysilicon gate resistance is similarly constrained: heavier doping helps but polysilicon's resistivity floor remains far higher than a metal's, and simply making gate lines wider to reduce resistance directly fights the density goals the entire scaling program exists to serve.

## 3. The Silicide Solution

The fix 1990s processes adopted was to react a deposited refractory metal with the exposed silicon or polysilicon surface to form a metal silicide layer directly on top of the gate and diffusion regions — titanium disilicide (TiSi2) in earlier deep submicron generations, cobalt disilicide (CoSi2) increasingly through the 1990s as geometries shrank further. A silicide layer has sheet resistance roughly an order of magnitude lower than heavily doped polysilicon or diffusion alone, because it behaves much more like a metal conductor than a doped semiconductor, while still forming a reliable, adherent, low-contact-resistance bond to the silicon beneath it.

## 4. Why Titanium Gave Way to Cobalt as Geometries Shrank Further

Titanium disilicide's formation process is sensitive to line width — on very narrow polysilicon lines, TiSi2 can fail to fully convert from its higher-resistance phase to its low-resistance phase, a line-width-dependent effect that gets worse exactly as lines get narrower through continued scaling. Cobalt disilicide does not share this narrow-line phase problem to the same degree, which is why later 1990s deep submicron generations, with their narrower gate lines, increasingly favored cobalt over titanium even though titanium silicidation was the more established, earlier-qualified process.