Deep Submicron CMOS Scaling 1990s Integrate Sidewall Spacers for Self Aligned Ldd Implants

# Deep Submicron CMOS Scaling (1990s): Step 4 — Integrate Sidewall Spacers for Self-Aligned LDD Implants

## 1. The Alignment Problem LDD Creates

Step 3 described two differently doped regions that need to sit at precise, nested lateral positions relative to the gate edge: the lightly doped implant close in, the heavily doped implant further out. Doing this with two separately masked lithography steps would require mask-to-mask alignment tolerances tighter than practical across a wafer, and any misalignment would defeat the entire purpose of grading the field in a controlled way. The 1990s process answer borrows a self-alignment trick rather than relying on lithographic precision: use the gate itself, plus a dielectric spacer grown or deposited against its sidewall, as the mask for each implant in turn.

## 2. The Spacer Process Flow

After the gate polysilicon is patterned, a first, light implant is done using the bare gate edge as the mask boundary — this places the lightly doped region immediately adjacent to the channel with no separate alignment step, since it is defined purely by the already-patterned gate. A conformal dielectric layer (commonly silicon dioxide or silicon nitride) is then deposited over the whole wafer and anisotropically etched back, leaving material only on the vertical sidewalls of the gate as a spacer of controlled width. A second, heavier implant then uses the combined gate-plus-spacer edge as its mask boundary, placing the heavily doped contact region further from the channel by exactly the spacer's thickness — a dimension controlled by deposition and etch process parameters, not by lithographic alignment at all.

## 3. Why Self-Alignment Matters for a Deep Submicron Process

Because both implant boundaries are defined relative to the same physical gate edge rather than to two independently aligned masks, the spacing between the lightly doped and heavily doped regions is reproducible to within the spacer-deposition process's own tight tolerances, which are far better than lithographic overlay tolerances at the dimensions 1990s processes were working at. This is the same self-aligned philosophy the `ion_implantation` series' earlier steps established for source/drain implants generally, extended here to a second, nested implant rather than a single one.

## 4. What the Spacer Width Controls

The spacer's thickness is itself a tunable process parameter: a wider spacer moves the heavily doped region further from the channel, further softening the field gradient at the cost of more added series resistance, while a narrower spacer trades some of that resistance back for a smaller reduction in peak field. Process engineers tune spacer width as one of the primary knobs for balancing Step 3's reliability-versus-speed trade for a given node's channel length and voltage.

Spacer Width Tunes the Reliability-Speed Trade hot-carrier lifetime and drive current against sidewall spacer width, same channel length and voltage hot-carrier lifetime (improves with wider spacer) drive current (degrades with wider spacer) process engineers pick a spacer width near this crossing region spacer width increases left to right wider spacer: more reliability margin, less raw speed — a tunable knob, not a fixed constant spacer width is set by deposition thickness and etch time, not lithography
Self-Aligned Implant Sequence the gate edge, then the gate-plus-spacer edge, define each implant boundary in turn GATE EDGE ALONE first, light implant — defines the lightly doped region's inner boundary SPACER DEPOSIT + ETCH conformal dielectric etched back to leave sidewall material only GATE + SPACER EDGE second, heavy implant — defines the contact region's inner boundary no separate lithography mask needed for the second implant's alignment

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