Deep Submicron CMOS Scaling 1990s Integrate the Self Aligned Salicide Process

# Deep Submicron CMOS Scaling (1990s): Step 8 — Integrate the Self-Aligned Salicide (SALICIDE) Process

## 1. Siliciding the Gate and the Diffusions Without Extra Masks

Step 7 established why both the polysilicon gate and the source/drain diffusions need a silicide layer to control sheet resistance. Doing this with separate masked silicidation steps for the gate and for each diffusion region would add lithography steps the deep submicron die's already-growing mask count (a cost the `bicmos_logic_1980s` series' step 5 already flagged as a general integration tax) could not comfortably absorb. The self-aligned silicide — salicide — process instead forms silicide simultaneously on the gate and on the source/drain regions using the same blanket metal deposition and anneal, with no additional patterning mask required for either.

## 2. How Self-Alignment Works Here

After the sidewall spacers from Step 4 are in place (themselves already serving the LDD implant), a blanket layer of titanium or cobalt is deposited over the entire wafer surface. A first anneal reacts the metal with any exposed silicon or polysilicon it directly contacts — the gate top and the exposed diffusion surfaces — while the metal sitting on top of the sidewall spacer's dielectric and on top of the field-oxide or trench-isolation regions does not react, because there is no silicon beneath it to react with. A selective wet etch then strips the unreacted metal everywhere it did not react, leaving silicide only where silicon was exposed — the gate top and the diffusion regions — and leaving the spacer and isolation surfaces bare. A second, higher-temperature anneal converts the silicide to its final low-resistance phase.

## 3. Why This Is the Same Self-Alignment Philosophy as the LDD Spacer

Just as Step 4's sidewall spacer used the gate's own geometry to define implant boundaries without a separate lithography mask, the salicide process uses the existing pattern of exposed silicon versus dielectric — already defined by the gate, spacer, and isolation structures from earlier process steps — to define where silicide forms, without a separate silicide mask. This is a recurring 1990s deep submicron theme: as mask count and alignment tolerance both become scarcer resources, process engineers increasingly favor structures that use an already-patterned feature to self-define a later step, rather than adding a new masked step for each new material or dopant that needs placing.

## 4. The Net Result at the Transistor Level

A finished salicided device has a low-resistance silicide cap on both the polysilicon gate (reducing gate-line RC delay, a concern that compounds with the interconnect RC issues Steps 10 and 11 of this series take up) and on the source/drain diffusions (reducing series resistance and improving the contact that subsequent tungsten-plug interconnect, covered in Step 9, lands on) — achieved with the same mask count the device needed before silicidation was added at all.

Mask Count Stays Flat While Silicide Coverage Grows process mask count against added functionality, salicide vs. a hypothetical separately-masked approach separately masked gate + diffusion silicidation (hypothetical) self-aligned salicide — same mask count throughout self-alignment avoids adding masks as coverage grows added silicide coverage: gate only, then gate + source/drain mask count is a scarce, costly resource at deep submicron geometries self-aligned structures are preferred wherever an existing pattern can define a new one
The Self-Aligned Silicide Process Flow four stages from blanket metal deposition to the finished silicide cap BLANKET METAL DEPOSIT titanium or cobalt covers the entire wafer uniformly FIRST ANNEAL + SELECTIVE ETCH reacts only where silicon is exposed, unreacted metal stripped away FINAL ANNEAL converts to the low-resistance silicide phase on gate and diffusions only no new lithography mask was used anywhere in this sequence

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